Semiconductor Air Spacer Formation for Low-Parasitic Gate Structures

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Solution Overview

Problem

Conventional methods of semiconductor fabrication struggle to reliably form air spacers, which are necessary to reduce parasitic capacitance and improve device performance in advanced ICs, due to their inability to achieve the desired size and shape suitable for modern FET devices.

Innovation Solution

A sacrificial layer, such as amorphous silicon or silicon germanium, is used to form air gaps by etching selectivity with dielectric gate spacers and gate structures, followed by a sealing layer to trap the air gaps as spacers, maintaining the integrity of other components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional fabrication methods are used, then manufacturing simplicity is maintained, but air spacers cannot be reliably formed with desired size and shape

Engineering Contradiction:
Improveair spacer formation reliabilityVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The fabrication process is divided into distinct stages: forming mandrels, depositing first spacers, forming second spacers, and removing mandrels. Each stage produces a specific structural component that accumulates to form the final air spacer structure, enabling precise control over the air spacer geometry and reliable formation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Mandrels are formed in advance before the actual air spacer structure is created. These preliminary mandrels serve as templates that guide the subsequent deposition of dielectric layers and formation of spacers, ensuring that air spacers achieve the desired size and shape with high reliability.

Inventive Principle:
Principle #10Preliminary action

2Speed

If air spacers are formed to reduce parasitic capacitance, then device speed is improved, but fabrication reliability deteriorates

Engineering Contradiction:
Improvedevice speedVSAvoidair spacer formation reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

Dielectric layers serve as intermediary materials between the mandrels and the final air spacer structure. The first and second dielectric layers are deposited conformally on mandrels and subsequently patterned to form spacers that define the air spacer geometry, enabling reliable formation through material properties and process control rather than direct air gap creation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The fabrication process controls the thickness and material properties of dielectric layers to precisely define air spacer dimensions. By adjusting deposition parameters, etch selectivity, and layer thicknesses, the process achieves reliable air spacer formation with controlled size and shape that reduces parasitic capacitance while maintaining fabrication reliability.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If geometry size is scaled down, then production efficiency is increased, but parasitic capacitance increases

Engineering Contradiction:
Improveproduction efficiencyVSAvoidparasitic capacitance
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

Air spacers are formed locally at critical locations where parasitic capacitance impacts performance, such as around gate structures and interconnect elements. By placing low-dielectric-constant air regions specifically where needed rather than throughout the entire device, the process reduces parasitic capacitance in high-impact areas while maintaining compact geometry for high production efficiency.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method allows for the reliable formation of air spacers with low dielectric constant, reducing parasitic capacitance and enhancing device speed, particularly in high-speed IC applications like ring oscillators, while being compatible with existing fabrication processes.

Implementation Method 1

A sacrificial layer, such as amorphous silicon or silicon germanium, is used to form air gaps by etching selectivity with dielectric gate spacers and gate structures

Methodology Applied
Scientific EffectEtching selectivity:

Implementation Method 2

followed by a sealing layer to trap the air gaps as spacers, maintaining the integrity of other components

Methodology Applied
Scientific EffectPhysical containment: Physical Containment

Data Source

PatentUS12356703B2Air spacer formation for semiconductor devices
Publication Date: 2025.07.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12356703B2 patent drawing
  • US12356703B2 patent drawing
  • US12356703B2 patent drawing

AI summary

A dummy gate is formed over a substrate. A sacrificial layer is formed over the dummy gate. An interlayer dielectric (ILD) is formed over the dummy gate and over the sacrificial layer. The dummy gate is replaced with a metal-containing gate. The sacrificial layer is removed. A removal of the sacrificial layer leaves air gaps around the metal-containing gate. The air gaps are then sealed.