Semiconductor Air Spacer Parasitic Capacitance Reduction

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Solution Overview

Problem

As semiconductor devices become more highly integrated, forming contact structures between increasingly complex wiring structures becomes difficult due to increased aspect ratios, leading to challenges in reducing parasitic capacitance and resistance.

Innovation Solution

A semiconductor device design featuring conductive structures with alternating contact structures, insulation structures with air gaps, and spacers, which include air spacers and insulating materials like silicon nitride and silicon oxide, to reduce parasitic capacitance by creating air spaces and gaps between conductive and insulation structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor devices are highly integrated, then device functionality and density are improved, but parasitic capacitance and resistance increase

Engineering Contradiction:
Improvedevice integration densityVSAvoidparasitic capacitance
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces air gaps (porous spaces) between conductive structures to reduce parasitic capacitance. Specifically, air gaps are formed between bit line structures and contact structures, allowing electrical field isolation while maintaining compact integration. This porous approach reduces unwanted electrical interactions without sacrificing integration density.

Inventive Principle:
Principle #31Porous materials

Solution Approach 2:

The patent uses air gaps as intermediary spaces between conductive elements. These air gaps act as dielectric mediators that reduce capacitive coupling between adjacent conductive structures (bit lines and contact structures), thereby reducing parasitic capacitance while allowing the structures to remain in close proximity for high integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If aspect ratios of wirings increase due to high integration, then device density is improved, but contact structure formation becomes difficult

Engineering Contradiction:
Improvedevice densityVSAvoidcontact structure formation
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent addresses the aspect ratio challenge by introducing horizontal air gaps between conductive structures at different vertical levels. This dimensional approach allows contact structures to be formed despite high aspect ratios, as the air gaps provide lateral separation that facilitates manufacturing processes while maintaining vertical integration density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If air gaps are introduced to reduce parasitic capacitance, then electrical properties are improved, but device complexity increases

Engineering Contradiction:
Improveelectrical propertiesVSAvoidwiring structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the wiring structure by introducing discrete air gaps between specific conductive elements (bit lines and contact structures). This segmentation approach reduces parasitic capacitance at critical interfaces while avoiding the need to redesign the entire wiring architecture, thus limiting the increase in overall device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies air gaps locally at specific locations where parasitic capacitance is most problematic (between bit lines and contact structures), rather than uniformly throughout the entire device. This localized approach improves electrical properties where needed while minimizing the added structural complexity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively reduces parasitic capacitance and contact resistance, enhancing the electrical properties of semiconductor devices by minimizing unwanted electrical interactions between conductive and contact structures.

Implementation Method 1

an air space may be provided between a conductive structure and a contact structure, and an air gap may be provided between the conductive structure and an insulation structure, to reduce a parasitic capacitance

Methodology Applied
Scientific EffectParasitic capacitance reduction: Capacitance

Data Source

PatentUS11417665B2Semiconductor devices
Publication Date: 2022.08.16 SAMSUNG ELECTRONICS CO LTD
  • US11417665B2 patent drawing
  • US11417665B2 patent drawing
  • US11417665B2 patent drawing

AI summary

A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.