Semiconductor Device With Aligned Side Surfaces for High Integration
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing size for increased storage capacity, lowering costs, and achieving a high number of write cycles without data loss when power is off, particularly due to issues with volatile memory devices like DRAM and flash memory, which suffer from short data holding periods and limited write cycles.
Innovation Solution
A semiconductor device with a novel three-dimensional structure where side surfaces of transistor components are aligned, allowing for high integration and using oxide semiconductors or widegap materials like silicon carbide, enabling a high degree of integration and unlimited write cycles without data loss when powered off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If flash memory is used to achieve nonvolatile storage with long data holding period, then data retention is improved, but the gate insulating layer deteriorates due to tunneling current after a predetermined number of writing operations
Solution Approach 1:
The patent changes the fundamental operating mechanism from tunneling current injection (flash memory) to charge transfer through a channel region (semiconductor device). This parameter change in the writing mechanism eliminates tunneling current damage to the gate insulating layer while maintaining nonvolatile data storage capability through charge accumulation in the channel formation region.
Solution Approach 2:
The patent extracts and removes the floating gate structure that causes tunneling current deterioration. By eliminating this component and using a simple gate electrode instead, the invention avoids the gate insulating layer degradation problem while achieving nonvolatile memory functionality through charge storage in the channel region.
2Quantity of substance
If three-dimensional integration of transistors is implemented to increase storage capacity per unit area, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar two-dimensional transistor layout to three-dimensional vertical integration. Multiple transistor layers are stacked above each other with shared source and drain electrodes, effectively utilizing the vertical dimension to increase storage capacity per unit area while maintaining relatively simple manufacturing processes.
Solution Approach 2:
The patent merges source and drain electrodes across multiple transistor layers, allowing shared electrical connections vertically. This consolidation reduces the number of discrete components and interconnections needed, managing device complexity while achieving high integration density through three-dimensional stacking.
Data Source
AI summary
An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode. A portion of a side surface of the semiconductor layer having the channel formation region and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other when seen from a planar direction.