Semiconductor Device with Aligned Third Layer for Mobility
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Solution Overview
Problem
Semiconductor devices with polysilicon channels face challenges in carrier mobility due to high density of grain boundaries, leading to decreased mobility, increased subthreshold slope, and threshold voltage shifts, which are exacerbated by random crystal orientations and high impurity concentrations.
Innovation Solution
The semiconductor device incorporates a third semiconductor layer with a higher orientation ratio and lower grain boundary density between the first and second semiconductor layers, aligning crystal grains parallel to the current flow direction to reduce carrier interactions with grain boundaries, and strategically positions the first electrode to minimize leakage and impurity diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a polysilicon channel is used in the semiconductor device, then the device can be manufactured with conventional processes, but the carrier mobility decreases due to high density of grain boundaries
Solution Approach 1:
The patent applies local quality by creating a specific semiconductor layer (third layer) with high orientation ratio and low grain boundary density in the channel region, while other layers may have different properties. This localized optimization of crystal orientation in the channel area improves carrier mobility without requiring changes to the entire semiconductor structure or manufacturing process
Solution Approach 2:
The patent uses a composite semiconductor structure with multiple layers having different crystal orientations and properties. The third semiconductor layer with high orientation ratio acts as a specialized channel layer, while other layers provide structural support and electrical connections, creating a composite material system that achieves both manufacturability and high performance
2Ease of manufacture
If random crystal orientations are present in the semiconductor layer, then the manufacturing process is simpler, but the carrier mobility decreases and threshold voltage shifts occur
Solution Approach 1:
The patent changes the crystal orientation parameter of the third semiconductor layer to have a high orientation ratio with crystal grains aligned parallel to the current flow direction. This parameter change from random orientation to aligned orientation improves carrier mobility and suppresses threshold voltage shifts while maintaining compatibility with conventional manufacturing processes
3Ease of manufacture
If grain boundary density is high in the semiconductor channel, then the manufacturing is easier, but the carrier mobility decreases and leakage current increases
Solution Approach 1:
The patent creates a third semiconductor layer with locally optimized properties including low grain boundary density and high orientation ratio in the channel region. This localized quality improvement reduces carrier scattering at grain boundaries, enhancing mobility and reducing leakage current while maintaining manufacturability through conventional processing
Solution Approach 2:
The patent promotes equipotentiality by aligning crystal grains parallel to the current flow direction, creating a more uniform electrical potential distribution across the channel. This alignment reduces potential variations caused by grain boundaries, leading to improved carrier mobility and reduced leakage current
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a first electrode. The third semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer. The first electrode opposes the third semiconductor layer. An orientation ratio of the third semiconductor layer is higher than an orientation ratio of the first semiconductor layer.