Semiconductor Package Alignment via Guide Holes and Substrate Structures
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Solution Overview
Problem
Accurate alignment of semiconductor chips and substrates in stacked semiconductor packages is challenging due to mechanical errors and process equipment issues, affecting the reliability of electrical connections.
Innovation Solution
Incorporating alignment structures that extend from the second substrate into guide holes of the first molding layer, allowing for precise alignment and electrical connection between substrates, even in cases of misalignment, through a reflow process that forms connection terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacking methods are used to achieve high integration, then the integration density is improved, but the alignment accuracy deteriorates
Solution Approach 1:
Guide holes are formed in the first molding layer before mounting the second substrate, and alignment structures are prepared in advance on the second substrate. These preliminary structures enable accurate alignment to be achieved during the stacking process by fitting the alignment structures into the guide holes, thereby resolving the alignment accuracy issue while maintaining high integration density
Solution Approach 2:
The guide holes in the first molding layer serve as intermediary alignment features that mediate between the first substrate and the second substrate. The alignment structures on the second substrate fit into these guide holes, providing a mechanical interface that ensures accurate positioning and alignment during the stacking process, thus improving alignment accuracy without compromising integration density
2Manufacturing precision
If alignment structures are added to improve alignment accuracy, then the manufacturing complexity increases
Solution Approach 1:
The alignment function is segmented into two separate components: guide holes formed in the first molding layer and alignment structures formed on the second substrate. This segmentation allows each component to be manufactured independently using existing processes, reducing overall manufacturing complexity while achieving improved alignment accuracy through their cooperative interaction
3Reliability
If guide holes are formed in the molding layer, then the alignment reliability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The formation of guide holes in the molding layer is merged with the existing molding process that creates the encapsulation structure. By combining these functions into a single manufacturing step, the alignment reliability is improved through the presence of guide holes, while the manufacturing process complexity is minimized as no separate operation is required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the reliability of stacked semiconductor packages by ensuring accurate alignment and electrical connection between substrates, improving structural stability and reliability of the package.
Implementation Method 1
through a reflow process that forms connection terminals
Data Source
AI summary
Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a first semiconductor chip on a first substrate, a first molding layer covering a sidewall of the first semiconductor chip and including at least two guide holes that expose the first substrate and are spaced apart from each other in a periphery of the first substrate, a second substrate on the first molding layer, a connection terminal between the first substrate and the second substrates and connecting the first and second substrates to each other, and an alignment structure that extends from a bottom surface of the second substrate into each of the at least two guide holes of the first molding layer. A height of the alignment structure is greater than a height of the first molding layer and the first semiconductor chip.