Semiconductor Package Alignment Guide Holes Protrusions
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Solution Overview
Problem
Current semiconductor packages face challenges in reliability due to misalignment and non-wetting issues during the reflow process, which can lead to warpage and affect the precision of solder connections between upper and lower solder balls.
Innovation Solution
The implementation of guide holes and protruding portions in the mold layer and interposer substrate, respectively, to prevent undesired shifting during the reflow process, ensuring precise alignment and connection of solder structures through the use of guide holes and protruding portions that fit together, and the application of an under-fill layer to seal and maintain space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If guide holes and protruding portions are added to prevent misalignment, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The guide holes in the mold layer and protruding portions on the interposer substrate automatically align with each other during the reflow process, enabling self-alignment without additional external fixtures or complex alignment mechanisms. The protruding portions fit into the guide holes to prevent undesired shifting, achieving precise alignment through the components' own structural features.
2Reliability
If the interposer substrate is positioned closer to the semiconductor chip, then connection reliability is improved, but manufacturing precision deteriorates due to alignment difficulty
Solution Approach 1:
The guide holes are pre-formed in the mold layer and the protruding portions are pre-formed on the interposer substrate before the reflow process. These preliminary structural preparations ensure that when the interposer substrate is positioned close to the semiconductor chip during reflow, the alignment is automatically maintained through the fitting of protruding portions into guide holes, preventing misalignment even at close distances.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip on a first substrate, a first mold layer provided on the first substrate to cover a side surface of the first semiconductor chip, a solder structure provided on the first substrate, and a second substrate provided on the solder structure. A guide receptacle is formed at one of a top surface of the first mold layer and a bottom surface of the second substrate, a first alignment protrusion is formed at the other of the top surface of the first mold layer and the bottom surface of the second substrate, and at least a portion of the first alignment protrusion is provided in the guide receptacle.