Semiconductor Package Alignment Keys and Wiring Patterns
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Solution Overview
Problem
The increasing demand for high integration and high-speed semiconductor elements poses challenges in maintaining process margins and alignment accuracy, particularly in exposure processes and bonding techniques, leading to defects such as gapfill defects and solder ball misalignment.
Innovation Solution
A semiconductor package design featuring a first and second semiconductor chip with distinct wiring structures, alignment keys, and bonding pads, where the alignment keys do not overlap the wiring patterns, enabling precise alignment and bonding through Cu—Cu hybrid bonding, eliminating the need for gapfill processes and reducing package thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high integration is implemented to increase semiconductor element density, then the number of elements per unit area increases, but process margin decreases and alignment accuracy deteriorates
Solution Approach 1:
The patent divides the chip structure into multiple layers (first chip layer, second chip layer) with distinct functional regions. Each layer contains specific elements (semiconductor elements, bonding pads, alignment keys) that are spatially segmented to avoid interference. This segmentation allows high integration density while maintaining manufacturing precision by separating critical alignment functions from dense element regions.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by placing a second chip layer above a first chip layer. This dimensional change enables increased element capacity without compromising two-dimensional alignment accuracy, as each layer can be independently aligned using alignment keys that extend through multiple layers.
2Quantity of substance
If high integration is implemented to increase semiconductor element density, then the number of elements per unit area increases, but exposure process margin decreases
Solution Approach 1:
The patent segments the chip into regions with different pattern densities. Alignment keys and bonding pads are positioned in lower-density regions, while semiconductor elements are concentrated in optimized-density regions. This segmentation allows the exposure process to maintain adequate process margins in critical areas while achieving high overall integration through strategic element placement.
3Ease of manufacture
If traditional bonding processes are used with overlapping alignment keys and wiring patterns, then alignment is simplified, but gapfill defects and solder ball misalignment occur
Solution Approach 1:
The patent extracts the alignment function from the wiring pattern area by positioning alignment keys in dedicated regions that do not overlap with active wiring patterns. This separation allows alignment to be performed independently without interfering with electrical connections, eliminating gapfill defects and solder ball misalignment while maintaining alignment ease.
Solution Approach 2:
The patent introduces alignment keys as intermediary structures that mediate between the alignment process and the wiring patterns. These alignment keys provide visible alignment targets without interfering with electrical functionality, as they are positioned to overlap with wiring patterns in the plan view but are structurally separated to prevent interference.
4Measurement precision
If alignment keys overlap wiring patterns, then alignment targets are readily visible, but gapfill defects and solder ball misalignment occur
Solution Approach 1:
The patent uses alignment keys as intermediary structures that provide visible alignment targets without causing bonding defects. The alignment keys are designed to be positioned at specific locations where they can be easily observed for alignment purposes while their structural configuration prevents interference with solder ball placement and gapfill processes.
Data Source
AI summary
A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.