Semiconductor Alignment Mark Design for Layer Misalignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing alignment mark designs for semiconductor devices are compromised during intermediate processing steps like chemical mechanical polishing and deposition, leading to misalignment and errors due to damage or distortion of the alignment marks, resulting in lower detection contrast and increased overlay misalignment.
Innovation Solution
Enhanced alignment mark designs featuring arrays of alignment marks with specific dimensions and separations, including columnar alignment marks and groupings, which minimize damage during processing by maintaining even layer formation and contrast, thereby reducing misalignment errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional alignment mark designs are used, then the alignment marks can be formed initially, but the integrity of the alignment marks is compromised during intermediate processing steps like CMP or deposition of thick layers
Solution Approach 1:
The alignment mark structure is designed with different regional properties: the mark body has sufficient height (150-250 nm) to maintain integrity during processing, while the separation distances are optimized differently in different directions (shorter first separation between adjacent marks, longer second separation between columns). This local differentiation allows the mark to resist damage during CMP and deposition while maintaining detectability.
Solution Approach 2:
The alignment marks are designed with pre-determined dimensions and separations before processing begins. The specific height range (150-250 nm) and separation distances are established in advance to prevent damage during subsequent intermediate processing steps, rather than attempting to repair or adjust marks after damage occurs.
2Reliability
If alignment marks are made more robust to prevent damage, then integrity is improved, but detection contrast may be reduced
Solution Approach 1:
The alignment mark parameters are precisely optimized: height between 150-250 nm, width between 1500-1700 nm, with specific separation distances. These parameter changes balance the competing requirements of robustness (sufficient height to resist damage) and detectability (appropriate dimensions for light diffraction and optical detection). The first separation is kept shorter than the second separation to maintain contrast while preventing damage.
3Ease of manufacture
If the alignment mark structure is simplified, then manufacturing is easier, but the ability to maintain even layer formation during processing is reduced
Solution Approach 1:
The alignment mark design uses a segmented array structure with multiple marks arranged in columns and rows, separated by specific distances. This segmentation allows each individual mark to maintain even layer formation independently while the overall array provides redundancy and robustness. The first and second separations create distinct zones that manage stress and material distribution during processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced alignment mark designs effectively prevent layer misalignment and damage during semiconductor processing, ensuring higher detection contrast and improved alignment accuracy by maintaining even layer formation and shape, thus reducing errors in layer alignment.
Implementation Method 1
light is radiated onto the wafer. The radiated light is diffracted by the alignment marks, and the diffraction pattern is detected.
Data Source
AI summary
Better alignment mark designs for semiconductor devices may substantially lessen the frequency of layer misalignment scanner alignment problems. Exemplary alignment mark designs substantially avoid or minimize damage during the fill-in and etching and chemical mechanical processing processes. Thus, additional processing steps to even out various layers or to address the misalignment problems may also be avoided.