Semiconductor Package Alignment Mark Protection
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Solution Overview
Problem
Current semiconductor device packaging methods face challenges in efficiently forming and aligning conductive pillars and redistribution structures during the manufacturing process, particularly at the wafer level, which can lead to issues like poor bonding strength and damage to alignment marks during etching processes.
Innovation Solution
The method involves forming a lower and upper redistribution structure with dielectric layers and conductive pillars, where alignment marks are protected by dielectric layers to prevent damage during etching, and a rectifying dielectric layer is used to ensure even coverage and strong bonding at the wafer edge, facilitating the formation of conductive vias and pillars for efficient semiconductor device packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If alignment marks are exposed during etching processes, then etching can be performed accurately, but alignment marks may be damaged
Solution Approach 1:
A dielectric layer is formed over the alignment marks before the etching process to protect them from damage. This preliminary protective action allows subsequent etching to proceed without compromising the alignment marks, resolving the contradiction between achieving accurate etching and preventing mark damage.
2Manufacturing precision
If dielectric layers are applied uniformly across the wafer, then coverage is consistent, but edge areas may have insufficient bonding strength
Solution Approach 1:
The patent applies a rectifying dielectric layer specifically at the edge portion of the wafer where bonding strength is insufficient. This localized application provides enhanced bonding strength at the critical edge area without affecting the uniform coverage achieved by the main dielectric layer, resolving the contradiction between uniform coverage and edge bonding strength.
3Productivity
If conductive pillars are formed at wafer level, then manufacturing efficiency is improved, but alignment and bonding precision becomes more difficult
Solution Approach 1:
Alignment marks are formed and protected in advance before the conductive pillar formation process. This preliminary preparation enables precise alignment during wafer-level parallel processing, maintaining high manufacturing precision while achieving the productivity benefits of wafer-level fabrication.
Data Source
AI summary
A semiconductor device package includes a lower redistribution structure, an upper encapsulated semiconductor device and an upper redistribution structure. The lower redistribution structure includes a first dielectric layer, a RDL, a second dielectric layer, and a second RDL. The first RDL is disposed on the first dielectric layer and includes a circuit portion and an alignment mark portion insulated from the circuit portion. The second dielectric layer is disposed on the first RDL, wherein the second dielectric layer covers the alignment mark portion. The second RDL is disposed on the second dielectric layer and electrically connected to the first RDL. The upper encapsulated semiconductor device is disposed on the lower redistribution structure. The upper redistribution structure is disposed on the upper encapsulated semiconductor device.