Semiconductor Alignment Mark Visibility via Multi-Layer Dot Pattern
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Solution Overview
Problem
The precision of detecting alignment marks in semiconductor chips is degraded due to variations in the material and thickness of the metal film and interlayer insulating film, affecting the contrast between the mark and background regions, leading to inconsistent visibility across different semiconductor wafers or chip regions.
Innovation Solution
A semiconductor device with an alignment mark formation region and an integrated circuit formation region, where a dot pattern is formed in the lower layer of the background region to reduce reflected light, improving contrast recognition by utilizing diffraction, interference, and scattering mechanisms, and ensuring the patterns are formed in the same layers as the wiring and element isolation regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a cross-shaped alignment mark is formed using metal film in the same layer as uppermost wiring, then the alignment mark can be formed with standard manufacturing processes, but the contrast between the mark and background region becomes sensitive to variations in film thickness and material properties, degrading detection precision
Solution Approach 1:
The patent introduces a vertical dimension by forming a dot pattern in a lower layer than the cross-shaped mark. This multi-layer configuration creates optical interference effects that enhance contrast, transforming a two-dimensional planar mark into a three-dimensional optical structure that is more robust to film thickness variations.
Solution Approach 2:
The patent changes the optical parameters of the background region by introducing a dot pattern with specific pitch and size parameters. This modifies the reflectivity and interference characteristics of the background, creating a consistent optical contrast that is less sensitive to variations in metal film thickness and material properties.
2Device complexity
If the alignment mark uses a simple cross-shaped pattern in a uniform background, then the manufacturing process is simple, but the visibility and contrast are inconsistent across different semiconductor wafers and chip regions
Solution Approach 1:
By adding a vertical layer dimension with dots positioned below the cross-shaped mark, the patent creates a multi-layer optical structure. This dimensional addition produces consistent interference patterns that improve visibility reliability across different wafers and chip regions without significantly complicating the manufacturing process.
Solution Approach 2:
The dot pattern acts as an intermediary optical element between the light source and the cross-shaped mark. It mediates the optical interaction by creating a consistent background reflectivity pattern that enhances the contrast and reliability of mark detection across varying manufacturing conditions.
3Productivity
If no additional patterns are formed in the background region, then the manufacturing process remains simple and fast, but the reflected light from the background reduces the contrast and visibility of the alignment mark
Solution Approach 1:
The patent segments the background region into multiple discrete dot patterns arranged in a periodic array. This segmentation approach creates optical interference effects that reduce background reflectivity and enhance mark contrast, while the regular periodic structure allows for efficient single-step manufacturing that maintains high productivity.
Solution Approach 2:
By introducing dot patterns with optimized parameters (pitch, size, density), the patent changes the optical properties of the background region. These parameter changes create constructive and destructive interference patterns that suppress background reflectivity and enhance the visibility of the alignment mark without adding complex multi-step manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the visibility of alignment marks across semiconductor chips, maintaining sufficient contrast for accurate camera recognition despite variations in film thickness, thereby improving positioning precision and manufacturing consistency.
Implementation Method 1
a first pattern is formed in a lower layer of the background region... utilizing diffraction, interference, and scattering mechanisms
Implementation Method 2
utilizing diffraction, interference, and scattering mechanisms
Implementation Method 3
utilizing diffraction, interference, and scattering mechanisms
Data Source
AI summary
To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.