Semiconductor Alignment Mark Profile Control via Selective Implantation
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Solution Overview
Problem
Conventional semiconductor device fabrication processes result in alignment marks with asymmetric profiles, leading to optical signal judgment problems and misalignment errors during photolithography, which reduce yield and device reliability.
Innovation Solution
A method involving the formation of doped and undoped regions in conductive layers within trenches on a semiconductor substrate, with specific etching selectivities, to create symmetric profiles for alignment marks, preventing misalignment errors during photolithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single side buried strap (SSBS) is used to electrically connect trench capacitor plate and source in conventional DRAM fabrication, then device density and integration are improved, but asymmetric profile is generated on testkey region causing optical signal judgment problems and misalignment errors
Solution Approach 1:
The substrate is divided into device region and testkey region, with different trench structures formed in each region. The testkey region trenches are designed to be symmetric while device region trenches can be asymmetric, allowing separate optimization of each region's function.
Solution Approach 2:
Different conductive layer structures are created in different regions: the device region has asymmetric conductive layers suitable for high-density integration, while the testkey region has symmetric conductive layers optimized for alignment mark functionality and optical signal quality.
2Ease of manufacture
If asymmetric profile alignment marks are formed in conventional processes, then device region fabrication is simplified, but optical signal judgment problems occur leading to yield reduction
Solution Approach 1:
The fabrication process is segmented into region-specific steps, allowing the testkey region to receive additional processing (second implantation) that creates symmetric profiles, while the device region follows the simpler conventional process.
Solution Approach 2:
The conductive layer in the testkey region undergoes parameter changes through a second implantation process that modifies its etching selectivity, creating a symmetric profile that resolves optical signal judgment problems while maintaining device region fabrication simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures symmetric profiles for alignment marks, enhancing fabrication yield and device reliability by preventing misalignment errors during photolithography processes.
Implementation Method 1
A conductive layer is next conformably formed in the first trench and in the second trench
Implementation Method 2
a first implantation process is performed in a first direction to form a first doped region with a first impurity in the conductive layer
Data Source
AI summary
A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.