Semiconductor Device Alignment Mark Placement in Stacked Body
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Solution Overview
Problem
In semiconductor device manufacturing, increasing the number of stacked layers to enhance integration and storage capacity leads to film stress, causing positional deviations and misalignment issues, which complicates alignment mark placement and measurement accuracy, thereby increasing costs and reducing efficiency.
Innovation Solution
The semiconductor device incorporates most alignment marks within the plug region extending from the upper to the lower end of the stacked body, allowing for improved measurement accuracy and cost reduction by shortening the distance to the memory cell array region without dedicated alignment mark regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked layers is increased to enhance integration and storage capacity, then the storage capacity is improved, but film stress causes positional deviations and misalignment issues
Solution Approach 1:
The patent transitions from two-dimensional planar alignment to three-dimensional alignment by placing alignment marks within the stacked body structure itself (in the depth dimension). This allows alignment marks to be positioned at multiple heights and locations within the stack, enabling more accurate measurement and compensation of positional deviations caused by film stress in high-layer-count devices.
2Ease of manufacture
If alignment marks are placed outside the stacked body, then the measurement process is simplified, but the distance to the memory cell array region increases and dedicated alignment mark regions are required
Solution Approach 1:
The patent merges the alignment mark function with the stacked body structure by placing alignment marks within the stacked body (e.g., on insulating films or at interfaces between conductive and insulating layers). This integration eliminates the need for separate dedicated alignment mark regions outside the stacked body, thereby reducing the overall area required while maintaining alignment functionality.
Solution Approach 2:
The stacked body structure serves multiple functions: it provides the memory cell array functionality, the insulation structure, and simultaneously hosts the alignment marks. This multi-functionality allows the same structural elements to serve both as functional components of the memory device and as reference markers for alignment, eliminating the need for separate alignment mark regions.
3Measurement precision
If alignment marks are placed within the plug region, then the distance to the memory cell array region is shortened and measurement accuracy is improved, but the plug region structure becomes more complex
Solution Approach 1:
The patent incorporates alignment marks within the stacked body structure during the early stages of fabrication, before the plug region is fully formed. This preliminary placement allows alignment marks to be positioned close to the memory cell array region from the outset, improving measurement accuracy without requiring additional complex structures in the plug region that would need to be added later.
Data Source
AI summary
According to one embodiment, in a semiconductor device, a stacked body is disposed above a substrate. In the stacked body, a conductive film and an insulating layer are alternately disposed in a stacking direction. A semiconductor columnar member penetrates the stacked body in a stacking direction. An insulating film surrounds the semiconductor columnar member. The insulating film penetrates the stacked body in the stacking direction. A pattern is disposed at a position adjacent to or close to a region. The region includes a penetration plug. The penetration plug extends from a position same as or above an upper end of the stacked body to a position below a lower end of the stacked body in the stacking direction. The pattern has a quadrangular or disjoined quadrangular shape.