Semiconductor Alignment Marks for 3D Wafer Stacking
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Solution Overview
Problem
Current methods for aligning semiconductor substrates in 3D wafer stacking are inaccurate and costly, requiring specialized hardware and additional processing steps, which hinders the formation of high-density 3D structures due to micron-scale variability and alignment inaccuracy.
Innovation Solution
The method involves forming apertures on one semiconductor substrate, bonding it to another, thinning to create optical contrast, and using these apertures as reference alignment marks for precise alignment of features on the backside, enabling accurate and cost-effective alignment without the need for complex tooling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional alignment methodologies are used for backside first-level alignment, then alignment can be achieved, but specialized hardware and additional processing are required, adding micron-scale variability and alignment inaccuracy
Solution Approach 1:
Alignment marks are formed on the front surface of the substrate before bonding occurs. This preliminary formation of alignment features eliminates the need for complex backside alignment hardware, as the marks are already in place to guide subsequent alignment operations after the substrates are bonded together.
Solution Approach 2:
The alignment marks are created as simplified optical features (such as opaque regions or contrast patterns) that replicate the function of complex alignment targets. These copied mark structures can be read by standard optical equipment rather than requiring specialized measurement hardware, thereby reducing device complexity while maintaining alignment accuracy.
2Manufacturing precision
If conventional alignment methodologies are used, then alignment can be performed, but micron-scale variability and alignment inaccuracy are introduced
Solution Approach 1:
The alignment marks are designed with optimized optical parameters including high contrast between mark and background, specific geometric patterns (such as L-shaped or cross-shaped markers), and controlled dimensions that maximize detection precision. These parameter optimizations enable sub-micron alignment accuracy and reduce variability by making the marks highly detectable and unambiguous to optical reading systems.
3Ease of manufacture
If backside plane is used for alignment, then alignment features can be formed, but the surface is initially without any features requiring additional processing
Solution Approach 1:
Instead of forming alignment features on the backside surface as conventionally done, the invention inverts the approach by forming alignment marks on the front surface of the substrate. This inversion allows the marks to be created during standard front-side processing operations, eliminating the need for separate backside alignment feature fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances alignment accuracy and reduces costs by allowing for high-density 3D structure formation with improved precision and efficiency in the manufacturing process.
Implementation Method 1
thin the first semiconductor substrate on a second surface of the first semiconductor substrate to a level to provide optical contrast between the apertures and the first semiconductor substrate
Data Source
AI summary
Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.