Semiconductor Alignment Pattern Using Peripheral Wiring
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Solution Overview
Problem
Conventional semiconductor devices face challenges in accurately aligning semiconductor integrated circuits due to low contrast alignment patterns, which reduces the number of circuits that can be formed on a substrate and becomes difficult to detect when the size of the circuits decreases, leading to inefficient use of space and detection issues.
Innovation Solution
The semiconductor device features an alignment pattern formed on the periphery of semiconductor integrated circuit forming areas, utilizing wiring patterns and guard rings to reflect sufficient light for precise detection by manufacturing apparatuses, thereby eliminating the need for separate alignment patterns and improving space efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If alignment patterns are formed on semiconductor integrated circuit forming areas, then detection precision is improved, but the number of semiconductor integrated circuits that can be formed is reduced
Solution Approach 1:
The alignment pattern is relocated from the planar area to the peripheral region surrounding the semiconductor integrated circuit forming areas. This spatial reconfiguration allows the alignment function to coexist with circuit formation without occupying valuable chip area, effectively utilizing the peripheral space that would otherwise be wasted.
Solution Approach 2:
The peripheral structure serves dual purposes: it acts as both the alignment pattern for detection and as part of the semiconductor device structure (such as guard rings or wiring). This multi-functionality eliminates the need for separate alignment patterns, maximizing the number of circuits that can be formed on the substrate.
2Quantity of substance
If alignment patterns are formed on scribe areas, then the number of semiconductor integrated circuits is improved, but detection precision deteriorates when scribe area width becomes small
Solution Approach 1:
Instead of confining the alignment pattern to the limited one-dimensional width of the scribe area, the alignment pattern is extended into the two-dimensional peripheral region surrounding the forming areas. This provides sufficient space for high-contrast patterns even when scribe areas are narrow, ensuring detection precision is maintained.
3Productivity
If scribe area width is reduced to improve space efficiency, then productivity is improved, but alignment pattern detection becomes difficult
Solution Approach 1:
The alignment pattern function is extracted from the scribe area and placed in the peripheral region. This separation allows the scribe area to be minimized for space efficiency while the alignment pattern resides in the peripheral space where it can maintain sufficient size and contrast for easy detection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for precise alignment and detection of the alignment pattern, even with small scribe areas, enhancing the accuracy of fuse pattern cutting and reducing production costs by integrating alignment functionality into existing structures.
Implementation Method 1
utilizing wiring patterns and guard rings to reflect sufficient light for precise detection by manufacturing apparatuses
Data Source
AI summary
A disclosed semiconductor device includes a semiconductor substrate including semiconductor integrated circuit forming areas; semiconductor integrated circuits formed on the semiconductor integrated circuit forming areas; and an alignment pattern formed on a periphery of at least one of the semiconductor integrated circuit forming areas.