Semiconductor Die Alignment Using Engineering Plastic Layer
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Solution Overview
Problem
Existing testing devices for semiconductor dies face challenges in achieving precise alignment and efficient cleaning of contact elements, particularly for singulated wafer-level chip-scale packages, due to issues with burr accommodation and contact element damage during alignment and contamination from silicon dust.
Innovation Solution
A testing apparatus comprising a nesting frame with an engineering plastic layer for smooth sliding and burr accommodation, reversible pogo pins for precise alignment, and a clean-out die with a polymer layer for cleaning, which reduces friction and prevents damage to redistribution layers while effectively collecting silicon dust and grit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a conventional sliding surface is used for die alignment, then the die can be positioned on the testing device nest, but friction causes damage to the redistribution layer and generates silicon dust contamination
Solution Approach 1:
The patent introduces an engineering plastic layer as an intermediary between the die and the bottom part. This layer has low friction properties that facilitate die sliding and alignment while protecting the die surface from direct contact, thereby preventing redistribution layer damage and reducing silicon dust generation.
Solution Approach 2:
The patent changes the friction parameter by replacing conventional sliding surfaces with an engineering plastic layer. This material has inherently lower friction coefficients, which enables smooth die positioning without causing damage or contamination to the contact elements.
2Strength
If burr is present on the die edge for mechanical strength, then the die structure is reinforced, but it interferes with precise alignment in the testing device nest
Solution Approach 1:
The patent extracts the burr from the alignment-critical area by providing a dedicated accommodation region in the nesting frame. This allows the burr to remain on the die for structural strength while being separated from the precision alignment zone, eliminating its interference with positioning accuracy.
Solution Approach 2:
The patent resolves the burr interference problem by transitioning from a two-dimensional alignment surface to a three-dimensional solution with a vertical accommodation region. The ledge creates a recessed space that captures the burr, allowing alignment to proceed in the horizontal plane without burr interference.
3Reliability
If contact elements are made reversible for non-destructive testing, then the testing process becomes non-invasive, but precise alignment and stable contact are more difficult to achieve
Solution Approach 1:
The patent applies beforehand cushioning by providing a compliant engineering plastic layer that cushions the contact between the die and the testing device. This layer compensates for minor alignment variations and ensures stable contact while maintaining the reversible, non-destructive nature of the testing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Facilitates precise alignment and easy cleaning of semiconductor dies, reducing contact element damage and contamination, and is specifically suitable for singulated wafer-level chip-scale packages.
Implementation Method 1
An engineering plastic layer on the bottom part forms a surface on which the semiconductor die slides during its alignment
Implementation Method 2
a clean-out die with a polymer layer for cleaning, which reduces friction and prevents damage to redistribution layers while effectively collecting silicon dust and grit
Data Source
Figure 1
Figure 2~3
Figure 4~5
AI summary
The testing apparatus for singulated semiconductor dies comprises a nesting frame (1) and a bottom part (2), which form a testing device nest adapted to the size of a semiconductor die (7). A pushing device (4) is provided for an alignment of the semiconductor die (7) in the testing device nest. An engineering plastic layer (3) on the bottom part (2) forms a surface on which the semiconductor die (7) slides during its alignment.