Semiconductor Alignment Marks for Stacked Device Inspection
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Solution Overview
Problem
Existing methods for inspecting alignment between semiconductor elements in stacked devices are inefficient, particularly when using internal alignment marks, as they become difficult to visualize and utilize when multiple chips are stacked.
Innovation Solution
The implementation of alignment marks on both upper and lower surfaces of semiconductor dies, which are imaged from the side to determine precise alignment or misalignment, using a system comprising holding sections, an imaging device, and a control section to correct misalignment during the stacking process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If internal alignment marks are used for measuring misalignment between semiconductor elements, then alignment measurement can be performed, but the alignment marks become difficult to visualize and utilize when multiple die or chips are stacked one above the other
Solution Approach 1:
The patent transitions from using internal alignment marks within the chip plane to using edge alignment marks positioned at the edges of stacked chips. This dimensional change allows the inspection apparatus to measure misalignment from the side of the stack, making the alignment marks visible and measurable even when multiple chips are stacked one above the other, thereby resolving the visibility issue while maintaining measurement precision.
2Productivity
If multiple semiconductor elements are stacked together to create high-density devices, then device functionality and integration are improved, but alignment quality determination between stacked elements becomes more difficult
Solution Approach 1:
The patent enables alignment quality determination in stacked devices by positioning alignment marks at the edges of chips and using a side-viewing inspection apparatus. This approach allows measurement of misalignment between stacked elements without interfering with the stacking process, thus maintaining high device integration density while enabling precise alignment quality determination.
Solution Approach 2:
The patent introduces edge alignment marks as intermediary features that facilitate alignment measurement between stacked semiconductor elements. These marks serve as mediators that can be visually detected from the side of the stack, enabling the inspection apparatus to determine alignment quality without directly measuring the bonded interfaces between chips.
3Measurement precision
If alignment marks are placed internally within chips, then alignment can be measured, but the marks cannot be effectively used when chips are bonded together for stacking
Solution Approach 1:
The patent repositions alignment marks from internal locations within the chip to the edges of the chip, enabling them to be viewed from the side of stacked chips. This dimensional repositioning makes the alignment marks adaptable to stacked device configurations, allowing alignment measurement to be performed on both individual chips and stacked assemblies using the same mark configuration.
Data Source
AI summary
An apparatus relating to the manufacture of stacked semiconductor devices includes, for example, a first holding section configured to hold a first semiconductor device and a second holding section configured to hold a second semiconductor device. Additionally, a measuring section including an imaging device for acquiring images of the first and second semiconductor devices and a control section configured to control the holding sections to correct misalignment between the semiconductor devices. The control section is further configured to determine misalignment using the images of the first and second semiconductor devices when the images include a first alignment mark disposed proximate to an edge of the first semiconductor device and a second alignment mark disposed proximate to an edge of the second semiconductor device.