Semiconductor Alignment via Topography on Intermediate Component
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Solution Overview
Problem
Existing semiconductor device fabrication methods face challenges in aligning optically opaque layers, as opaque materials like metals block optical signals, leading to difficulties in overlay and alignment during lithography processes, and recessing interlayer dielectric can result in defects and process variations.
Innovation Solution
Creating a raised area of topography over an alignment assisting marker using a hard mask layer on the semiconductor device, which allows for successful alignment and overlay through opaque metal and memory stack material layers by providing detectable surface topography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If opaque materials like metals are used in interconnect layers, then electrical conductivity is improved, but optical signal transmission is blocked making alignment difficult
Solution Approach 1:
The patent introduces an intermediary alignment marker structure that is optically detectable and positioned in a non-memory region. This marker serves as a mediator between the opaque metal interconnect layer and the alignment system, allowing optical detection without compromising the electrical functionality of the metal layer. The marker is deposited on top of the metal interconnect but in a separate alignment-only region.
Solution Approach 2:
The patent segments the device into functional memory regions and separate alignment-assisting regions. The alignment marker is placed in a non-memory region, separating the electrical functionality (metal interconnect in memory region) from the optical detection functionality (alignment marker in non-memory region). This segmentation allows each region to optimize its primary function without interference.
2Difficulty of detecting and measuring
If alignment markers are formed by recessing interlayer dielectric, then alignment visibility is improved, but defects and process variations increase
Solution Approach 1:
Instead of modifying the interlayer dielectric to create alignment markers, the patent copies the alignment marker pattern onto a separate deposited layer (such as a metal or dielectric layer) in the non-memory region. This copying approach avoids the complex and variable recessing process while maintaining clear optical visibility of the alignment markers.
Solution Approach 2:
Rather than removing material (recessing) to create visibility, the patent adds material (deposits alignment marker layers) to create the alignment features. This inversion of the approach - adding rather than removing - simplifies the process and reduces variability while achieving the same visibility goal.
3Measurement precision
If alignment markers are placed over metal interconnect, then alignment accuracy is improved, but optical detection is blocked by opaque materials
Solution Approach 1:
The patent resolves the optical blocking issue by moving the alignment marker formation to a different dimensional location - specifically, in a non-memory region above the metal interconnect. This spatial relocation in the vertical dimension allows the alignment markers to be optically accessible without requiring optical penetration through the opaque metal layers in the memory region.
Data Source
AI summary
An intermediate semiconductor device structure includes a first area including a memory stack area and a second area including an alignment mark area. The intermediate structure includes a metal interconnect arranged on a substrate in the first area and a first electrode layer arranged on the metal interconnect in the first area, and in the second area. The intermediate structure includes an alignment assisting marker arranged in the second area. The intermediate structure includes a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area and on the metal interconnect in the first area. The intermediate structure includes a hard mask layer arranged on the second electrode area. The hard mask layer provides a raised area of topography over the alignment assisting marker. The intermediate structure includes a resist arranged on the hard mask layer in the first area.