Semiconductor Die Alignment via Zigzag Circuit Patterns
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Solution Overview
Problem
Existing systems for maintaining alignment during the attachment of a semiconductor die to a circuit board are inadequate, leading to misalignment issues that affect the electrical and mechanical connection between bumps and circuit patterns.
Innovation Solution
The use of a semiconductor device configuration with nonconductive paste and specific circuit pattern arrangements, such as increased width and zigzag or crossed shapes, to enhance alignment during thermal compression bonding, ensuring precise alignment between the semiconductor die and the circuit board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional alignment systems are used during semiconductor die attachment, then the attachment process can be completed, but misalignment between bumps and circuit patterns occurs reducing connection reliability
Solution Approach 1:
The patent introduces a circuit board with extended circuit patterns that act as an intermediary alignment reference system. The extended patterns provide additional alignment margins and reference points that mediate between the die bump positions and the standard circuit patterns, compensating for misalignment without requiring perfect precision in the attachment process
Solution Approach 2:
The circuit patterns are segmented into standard portions and extended portions, where the extended portions serve as dedicated alignment buffers. This segmentation allows the alignment function to be separated from the signal transmission function, enabling the extended patterns to absorb misalignment while the standard patterns maintain their original signal integrity
2Manufacturing precision
If circuit patterns are extended to improve alignment tolerance, then alignment robustness increases, but device complexity and area increase
Solution Approach 1:
The extended circuit patterns serve multiple functions simultaneously: they provide alignment reference points, act as signal transmission paths, and function as mechanical support structures. This multi-functionality reduces the need for separate dedicated alignment features, thereby limiting the increase in device complexity while achieving improved alignment robustness
3Manufacturing precision
If circuit patterns are extended to improve alignment tolerance, then alignment robustness increases, but the area occupied by the circuit board increases
Solution Approach 1:
The circuit patterns are extended only in specific local regions where alignment sensitivity is highest, rather than uniformly across the entire circuit board. This localized extension provides alignment robustness where needed while minimizing the overall area increase, as the extensions are concentrated in critical alignment zones rather than distributed throughout the entire device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces misalignment, with 89.69% of samples showing satisfactory alignment, and minimal unacceptable misalignment, thereby improving the reliability of semiconductor device connections.
Implementation Method 1
enhance alignment during thermal compression bonding
Data Source
AI summary
Provided is a semiconductor device in which misalignment between a semiconductor die and a substrate (e.g., a circuit board) can be prevented or substantially reduced when the semiconductor die is attached to the circuit board. In a non-limiting example, the semiconductor device includes: a semiconductor die comprising at least one bump; and a circuit board comprising at least one circuit pattern to which the bump is electrically connected. In a non-limiting example, the circuit board comprises: an insulation layer comprising a center region and peripheral regions around the center region; a plurality of center circuit patterns formed in the center region of the insulation layer; and a plurality of peripheral circuit patterns formed in the peripheral regions of the insulation layer. The center circuit patterns may be formed wider than the peripheral circuit patterns, formed in a zigzag pattern, and/or may be formed in a crossed shape.