Semiconductor Device With Alternating Source And Body Tie Regions
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Solution Overview
Problem
Conventional semiconductor devices with source and body lead-out regions arranged in a strip configuration along the length of a conductive channel result in a large device size and conduction characteristic issues due to parasitic NPN transistor activation, primarily caused by inadequate implantation in the body lead-out region.
Innovation Solution
The semiconductor device features source and body lead-out regions alternately arranged in the width direction of a conductive channel, with a conductive auxiliary region of the same conductivity type as the source region, positioned on the boundaries, to reduce device length and optimize current flow, and a method involving ion implantation and thermal diffusion to form these regions using a shared photolithography mask.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If source region and body lead-out region are arranged in strip configuration along length direction of conductive channel, then device structure is simple, but device size in length direction becomes large
Solution Approach 1:
The patent transitions from a conventional linear arrangement along the channel length to an alternating arrangement in the width direction, effectively utilizing the transverse dimension to reduce the device's length while maintaining functional integrity
Solution Approach 2:
The device is segmented into alternating source regions and body lead-out regions arranged in a transverse pattern, allowing parallel current paths that reduce the effective length requirement while maintaining structural simplicity
2Ease of manufacture
If source region and body lead-out region are arranged in strip configuration, then manufacturing process is conventional, but conduction characteristics deteriorate due to parasitic NPN transistor activation
Solution Approach 1:
The patent introduces a conductive auxiliary region with specific conductivity type positioned adjacent to the body lead-out region, creating localized electrical characteristics that prevent parasitic NPN transistor activation while maintaining overall manufacturing conventionalness
Solution Approach 2:
The conductive auxiliary region acts as an intermediary element between the body lead-out region and the substrate, mediating the electrical interaction to prevent harmful parasitic effects while allowing the manufacturing process to remain conventional
3Length of moving object
If device size is reduced by alternating arrangement, then device length decreases, but implantation precision requirement increases
Solution Approach 1:
The conductive auxiliary region is formed through preliminary ion implantation before final device fabrication, establishing the necessary electrical characteristics in advance to guide subsequent processing steps and ensure precise region formation
Solution Approach 2:
The shared photolithography mask serves multiple functions: defining well regions, source regions, body lead-out regions, and conductive auxiliary regions simultaneously, reducing the number of alignment-critical steps while maintaining implantation precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the device size in the length direction, enhances current path efficiency, and mitigates conduction losses by ensuring proper implantation and preventing parasitic NPN transistor activation, thereby improving the Rdson of the device.
Implementation Method 1
implanting ions of a first conductivity type and ions of a second conductivity type into the substrate through the well region implantation window
Implementation Method 2
performing a thermal diffusion such that the implanted ions of the second conductivity type forms a well region, and the implanted ions of the first conductivity type forms a second region
Data Source
AI summary
A semiconductor device comprises: a substrate; a well region provided in the substrate, having a second conductivity type; source regions having a first conductivity type; body tile regions having the second conductivity type, the source regions and the body tie regions being alternately arranged in a conductive channel width direction so as to form a first region extending along the conductive channel width direction, and a boundary where the edges of the source regions and the edges of the body tie regions are alternately arranged being formed on two sides of the first region; and a conductive auxiliary region having the first conductivity type, provided on at least one side of the first region, and directly contacting the boundary, a contact part comprising the edge of at least one source region on the boundary and the edge of at least one body tie region on the boundary.