Semiconductor Device Amorphous Layer Contact Resistance
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Solution Overview
Problem
In semiconductor manufacturing, the small size of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) leads to a 'short channel effect' due to reduced gate length, and the conventional self-aligned silicide process faces challenges in forming titanium-silicon (TiSi) at the bottom of contacts, resulting in inhomogeneous amorphous layers and affecting electrode growth and device performance.
Innovation Solution
A semiconductor device manufacturing method involving epitaxial growth of electrodes with an amorphous layer, followed by forming cavities, dielectric layers, and conductive adhesive layers to create contact holes, where an annealing process forms titanium-silicon (TiSi) at the contact bottom, improving the silicide process and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of MOSFET is reduced to improve integration level and lower manufacture cost, then the integration level is improved, but the short channel effect occurs due to reduced gate length
Solution Approach 1:
The patent transitions from planar MOSFET to FinFET structure, adding vertical dimension by forming semiconductor fins. The channel region is formed in the fin structure, allowing gate to control channel from three sides (top, front, back), effectively increasing gate control without reducing horizontal dimensions, thus maintaining threshold voltage control while achieving higher integration density.
Solution Approach 2:
The patent employs composite material structure with semiconductor fin (silicon or silicon-germanium), gate electrode, and dielectric layers. The fin structure combines crystalline semiconductor with controlled doping regions, creating a composite architecture that enhances gate control and reduces short channel effects while enabling smaller device footprint.
2Ease of manufacture
If ion implantation is conducted to form amorphous layer before adhesive layer formation, then the energy needed to form TiSi is lowered, but the small diameter and large depth of contact hinder the ion implantation process and result in in-homogeneous amorphous layer
Solution Approach 1:
The patent performs preliminary epitaxial growth of semiconductor material in cavities formed on opposing sides of the gate structure, creating amorphous layers before contact hole formation. This preliminary action ensures uniform amorphous layer deposition across the entire surface, avoiding the penetration issues of ion implantation into deep, narrow contact holes. The amorphous layer is then exposed through subsequently formed contact holes, ensuring homogeneity throughout the layer.
Solution Approach 2:
Instead of attempting to penetrate vertically into deep contact holes via ion implantation, the patent forms amorphous layers in the horizontal plane through epitaxial growth on cavity surfaces, then accesses these layers through contact holes. This dimensional approach change ensures uniform layer formation without the geometric constraints of deep, narrow hole penetration.
3Ease of manufacture
If ion implantation is used to form amorphous layer, then TiSi formation energy is reduced, but the process adversely affects electrode growth and device performance due to in-homogeneous amorphous layer
Solution Approach 1:
The patent performs preliminary epitaxial growth of amorphous layers in cavities before contact formation, ensuring uniform layer deposition. This preliminary action creates homogeneous amorphous layers that serve as reliable bases for subsequent TiSi formation and electrode growth, eliminating the inhomogeneity problems caused by ion implantation while maintaining low formation energy through controlled thermal processes.
Solution Approach 2:
The patent replaces the mechanical ion implantation process with thermal epitaxial growth for forming amorphous layers. This substitution eliminates the geometric constraints and inhomogeneity issues of ion implantation into deep contact holes, while still achieving low-energy TiSi formation through controlled thermal annealing processes that promote uniform material deposition and reaction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the control over the channel region, reduces contact resistance, and improves the overall performance of the semiconductor device by directly forming TiSi on the amorphous layer, addressing the short channel effect and inhomogeneous layer issues.
Implementation Method 1
epitaxially growing electrodes in the cavities, with each electrode comprising an electrode body and an amorphous layer on the electrode body
Implementation Method 2
an annealing process forms titanium-silicon (TiSi) at the contact bottom
Data Source
AI summary
A semiconductor device and its manufacturing method are presented, relating to semiconductor technology. The manufacturing method comprises: providing a substrate structure comprising a substrate, a source region on the substrate, and a gate structure on the source region; forming cavities on two opposing sides of the gate structure; epitaxially growing electrodes in the cavities, with each electrode comprising an electrode body and an amorphous layer on the electrode body; forming an dielectric layer on the substrate structure covering the electrodes and the gate structure; etching the dielectric layer to form a contact hole exposing the amorphous layer; forming a conductive adhesive layer on the bottom and on the side of the contact hole; and forming a contact component on the conductive adhesive layer filling the contact hole. In this semiconductor device, the adhesive layer may be directly formed on the amorphous layer, resulting in improved performance of the device.