Semiconductor Analog Digital Delay Matching
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Solution Overview
Problem
In semiconductor devices with both analog and digital circuits, operational speed mismatches occur due to changes in power supply voltage, potentially leading to failure in normal operation as analog circuits' speeds are more dependent on power supply voltages than digital circuits', causing timing control issues.
Innovation Solution
A semiconductor device configuration where the digital circuit detects the delay variation in the analog circuit and generates a control signal to match the delay variation, using a detecting circuit and a second delay circuit connected to a less variable power supply potential to correlate and control the delay variations, ensuring the digital circuit's delay matches the analog circuit's delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the power supply voltage is increased to improve the operational speed of the analog circuit, then the operational speed of the analog circuit is improved, but the operational speed of the digital circuit becomes excessively high relative to the analog circuit, causing a speed mismatch
Solution Approach 1:
The patent applies dynamics by making the delay time of the digital circuit variable rather than fixed. The delay circuit adjusts its delay time dynamically based on the operational speed of the analog circuit, allowing the digital circuit's timing to adapt to analog circuit speed variations caused by power supply voltage changes. This resolves the speed mismatch while maintaining reliable operation.
Solution Approach 2:
The patent changes the delay time parameter of the digital circuit to match the operational speed characteristics of the analog circuit. By adjusting the delay time in response to power supply voltage variations, the system maintains proper timing relationships between digital control signals and analog circuit operations, preventing operational failures.
2Reliability
If the delay time of the digital circuit is increased to match the analog circuit's delay, then the timing synchronization is improved, but the overall operational speed of the digital circuit decreases
Solution Approach 1:
The delay time is made dynamic rather than statically increased. The delay circuit adjusts its delay time only when necessary to match the analog circuit's operational speed, rather than maintaining a constantly increased delay. This allows the digital circuit to operate at high speed when synchronization is not critical, while providing timing synchronization when needed.
3Device complexity
If a fixed delay circuit is used in the digital circuit, then the circuit complexity is reduced, but the timing mismatch with the analog circuit cannot be compensated for
Solution Approach 1:
The patent implements feedback by detecting the operational speed of the analog circuit and using this information to adjust the delay time of the digital circuit. The feedback mechanism monitors power supply voltage variations and corresponding analog circuit speed changes, then compensates by adjusting digital circuit timing, maintaining accurate timing control without excessive complexity.
Data Source
AI summary
A semiconductor device includes an analog circuit with a first delay variation in response to a variation in a power supply potential, and a digital circuit with a second delay variation smaller than the first delay variation. The analog circuit is connected to a first power supply potential. The digital circuit includes a detecting circuit detecting a first delay caused by a first circuit connected to the first power supply potential, and a second circuit generating a control signal to control the analog circuit, the second circuit being connected to a second power supply potential whose potential variation is smaller than the first power supply potential. A second delay caused by the second circuit is controlled in correlation to the first delay.