Semiconductor Assembly Antenna Orientation for Package Thickness

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Solution Overview

Problem

The semiconductor industry faces challenges in designing antenna elements for system-in-package (SiP) that balance radiation performance, electrical performance, and package size, particularly as packages shrink, due to issues with dielectric layer thickness and coupling capacitance affecting antenna performance.

Innovation Solution

A semiconductor assembly is designed with a wiring structure, a semiconductor die, and an electronic element featuring a first metal layer and a second metal layer perpendicular to the wiring structure's surface, with a dielectric material in between, allowing for independent control of the dielectric layer's thickness to optimize radiation performance without increasing the package thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the dielectric layer thickness is increased to improve radiation performance of the antenna element, then the radiation performance is improved, but the overall package thickness increases

Engineering Contradiction:
Improveradiation performanceVSAvoidpackage thickness
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent changes the orientation of the antenna element from a planar configuration within the package substrate to a three-dimensional configuration where the antenna element extends vertically outward from the package surface. The radiating element is positioned above the package substrate with the dielectric layer arranged perpendicular to the substrate, allowing the radiating dimension to be separated from the package thickness dimension. This enables independent optimization of radiation performance without increasing package thickness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the antenna element size is increased to improve radiation performance, then the radiation performance is improved, but the total package size increases

Engineering Contradiction:
Improveradiation performanceVSAvoidpackage size
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

The antenna element is reconfigured to extend in the vertical dimension above the package substrate rather than expanding horizontally within the package footprint. This allows the radiating length to be achieved without increasing the package area, effectively trading horizontal space for vertical space.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The antenna element is integrated into the package structure by nesting it within the existing package footprint. The base of the antenna element is supported by the package substrate, and the radiating portion extends upward, utilizing the vertical space above the package rather than requiring additional horizontal space.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Volume of moving object

If the dielectric layer is positioned within the package substrate to maintain compact size, then the package size is reduced, but undesired coupling capacitance increases

Engineering Contradiction:
Improvepackage sizeVSAvoidcoupling capacitance
Core Design Contradiction:
Volume of moving objectVSObject-generated harmful factors

Solution Approach 1:

The dielectric layer is extracted from its traditional position within the package substrate and repositioned to surround the antenna element externally. The dielectric material is arranged in a configuration that isolates the antenna element from the package substrate, preventing direct capacitive coupling between the antenna and substrate circuits while maintaining a compact overall package size.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11101541B2Semiconductor assembly and method for manufacturing the same
Publication Date: 2021.08.24 ADVANCED SEMICON ENG INC
  • US11101541B2 patent drawing
  • US11101541B2 patent drawing
  • US11101541B2 patent drawing

AI summary

A semiconductor assembly includes a first wiring structure, a first semiconductor die and a first electronic element. The first wiring structure has a first surface. The first semiconductor die is disposed on the first surface of the first wiring structure. The first electronic element is electrically connected to the first wiring structure. The first electronic element includes a first metal layer, a second metal layer and a dielectric material interposed between the first metal layer and the second metal layer. The first metal layer and the second metal layer are substantially perpendicular to the first surface of the first wiring structure.