Semiconductor Anti-Fuse Structure with Shared Control Gate
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Solution Overview
Problem
Conventional 1T1C semiconductor structures occupy a large area, making it challenging to achieve high density memory cells or redundancy, as each anti-fuse requires a separate control gate.
Innovation Solution
A method is developed to manufacture semiconductor structures with anti-fuse structures by forming a trench in a substrate, creating an isolation structure with a conductive element embedded within, and separating transistors from the conductive structure using an upper and lower isolation structure, allowing for compact anti-fuse formation between transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 1T1C structure is used for each anti-fuse, then each anti-fuse can be controlled independently, but the area occupied increases significantly
Solution Approach 1:
The patent merges multiple anti-fuse control functions into a single shared control gate structure. The control gate is positioned over the trench containing multiple anti-fuse elements, allowing one control gate to control multiple anti-fuses simultaneously. This combining approach reduces the number of control gates needed and shrinks the unit cell area while maintaining independent controllability of each anti-fuse through selective voltage application.
Solution Approach 2:
The patent transitions from a planar 1T1C configuration to a three-dimensional structure where anti-fuse elements are stacked vertically within a trench beneath a shared control gate. This vertical arrangement in the depth dimension allows multiple anti-fuses to share the same lateral footprint, significantly reducing the area occupied by each unit cell while preserving independent control through voltage modulation.
2Quantity of substance
If the number of anti-fuse is increased for high density memory or redundancy, then memory capacity or redundancy improves, but the overall device area expands
Solution Approach 1:
The patent nests multiple anti-fuse elements vertically within a single trench structure, similar to nested dolls. The anti-fuse elements are stacked one above another in the vertical dimension, sharing the same lateral space. This nesting approach allows a high number of anti-fuses to be packed into a compact volume, increasing memory density without proportionally increasing the device area.
Solution Approach 2:
The patent exploits the vertical dimension by stacking anti-fuse elements beneath a shared control gate in three-dimensional space. This vertical stacking enables a large quantity of anti-fuses to be accommodated within a small lateral footprint, achieving high density memory and redundancy capabilities without expanding the overall device area proportionally.
3Area of stationary object
If trench width is reduced to minimize area, then device density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the isolation function by introducing a dedicated isolation structure within the trench that separates the conductive element from the source/drain regions. This segmentation allows the trench to be narrower while still providing adequate isolation, as the isolation structure is precisely positioned within the trench rather than requiring the entire trench width to provide isolation. This reduces the lateral space needed while maintaining manufacturing feasibility.
Solution Approach 2:
The patent introduces an isolation structure as an intermediary element within the trench that mediates between the conductive element and the source/drain regions. This intermediary isolation structure provides the necessary electrical separation in a compact configuration, enabling narrower trench widths without compromising isolation effectiveness or manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the size of semiconductor structures with anti-fuse structures, enabling higher device density by allowing multiple anti-fuses to share the same control gate, thus minimizing the overall area occupied.
Implementation Method 1
The exposed sidewall of the substrate is oxidized to form an upper isolation structure on the lower isolation structure
Data Source
AI summary
A method of manufacturing a semiconductor structure including following operations is provided. A substrate extending along a first direction is provided. A trench crossing the substrate is then formed to define a first active region and a second active region. A lower isolation structure is formed in the trench, in which the lower isolation structure exposes a portion of a sidewall of the substrate. The exposed sidewall of the substrate is oxidized to form an upper isolation structure on the lower isolation structure, in which the upper isolation structure extends into the substrate. A conductive structure embedded in the upper isolation structure is formed. A first transistor and a second transistor are respectively formed in the first active region and the second active region.