High Voltage Semiconductor Arc Suppression via SF6 Recess
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Solution Overview
Problem
Conventional packaging materials for high voltage semiconductor devices, such as Thermoset, have low dielectric breakdown voltages, making them prone to electric arcing and device failure as device sizes decrease and voltage magnitudes increase, especially with reduced spacing between conductors.
Innovation Solution
Incorporating a high voltage electric arc suppression material, such as SF6, within the semiconductor device package in a recess adjacent to the chip to prevent arcing, using materials like metal, metal-coated plastic, or ceramic packages that can withstand high temperatures and include a submount for the chip, with wire leads electrically coupled to the chip and suppression material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging materials like Thermoset are used, then the device structure is simple and easy to manufacture, but the dielectric breakdown voltage is low causing electric arcing at high voltages
Solution Approach 1:
The packaging structure is divided into multiple functional zones: a recess region containing the semiconductor chip and arc suppression material, and an outer packaging body. This segmentation allows the arc suppression material to be localized where it is most needed (near the chip and wire leads) without requiring the entire package to have high dielectric properties, thus maintaining reliability while controlling complexity
Solution Approach 2:
An electric arc suppression material (such as SF6 gas or ceramic beads) is introduced as an intermediary substance between the high-voltage wire leads and the package wall. This intermediary material has high dielectric breakdown voltage properties that prevent electric arcing, solving the reliability problem without requiring the base packaging material itself to have extremely high dielectric strength
2Productivity
If device size is reduced and spacing between conductors is decreased, then productivity and integration are improved, but the likelihood of electric arcing increases
Solution Approach 1:
The arc suppression material is placed locally in the recess region surrounding the chip and wire leads, where electric fields are most concentrated and arcing is most likely to occur. This localized approach provides high dielectric protection exactly where needed, enabling miniaturization of the overall device while maintaining arc resistance in the critical high-stress regions
3Power
If high voltage operation is implemented, then power capability is improved, but electric arc suppression becomes more difficult with conventional materials
Solution Approach 1:
The packaging system uses a composite structure combining conventional packaging materials (metal, plastic, or ceramic) with specialized arc suppression materials (SF6 gas, ceramic beads, or other high-dielectric substances). This composite approach allows the base package to provide mechanical protection while the specialized material provides high-voltage arc suppression, enabling safe operation at high voltages up to 1700V and above
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of high voltage electric arc suppression materials effectively reduces the likelihood of electric arcs, ensuring reliable operation even at high voltages by maintaining a sufficient dielectric breakdown voltage and preventing arcing between conductors and package surfaces.
Implementation Method 1
a high voltage electric arc suppression material can be in the recess which can be a liquid or gas material having a dielectric breakdown voltage sufficient to prevent an electric arc from the wire lead to the submount
Data Source
AI summary
A high voltage semiconductor device can include a high voltage semiconductor device package that includes a wall defining a recess within the high voltage semiconductor device package. A high voltage semiconductor chip can be in the recess and a high voltage electric arc suppression material can be in the recess.