Semiconductor Array Contact Line Layout for Lower Contact Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices, such as DRAM, become more miniaturized, the resistance of connecting plugs in through holes increases, affecting the operating current and electrical performance due to thickness differences between array and peripheral regions, making the semiconductor manufacturing process more difficult and increasing contact resistance in the array region.
Innovation Solution
A method involving forming a groove in the dielectric layer parallel to the substrate surface in the array region and filling it with a conductive material to create an array contact line, which reduces contact resistance and improves electrical performance by increasing the process window and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-hole plugs are used to connect external electrical signals in the array region, then electrical connection is achieved, but contact resistance increases and electrical performance deteriorates
Solution Approach 1:
The patent transitions from vertical through-hole plugs to a horizontal/linear array contact line structure that extends along the dielectric layer. This dimensional change allows the contact line to achieve better electrical contact with the semiconductor structure while reducing contact resistance, as the linear configuration provides a larger contact area and more favorable current distribution path.
Solution Approach 2:
The array contact line is formed by dividing the dielectric layer into segments (grooves) that are filled with conductive material. This segmentation approach creates multiple contact points along the linear structure, effectively reducing overall contact resistance by distributing the electrical connection across multiple locations rather than relying on a single through-hole plug.
2Ease of manufacture
If conventional manufacturing processes are used for through-hole plugs, then connection structure is formed, but manufacturing complexity increases due to thickness differences between array and peripheral regions
Solution Approach 1:
The array contact line structure serves multiple functions: it provides electrical connection in the array region, accommodates the thickness differences between array and peripheral regions, and simplifies the manufacturing process. The linear groove-based structure can be formed using standard semiconductor fabrication techniques that are already widely used, making it universally applicable without requiring specialized complex processes.
Solution Approach 2:
The patent changes the geometric parameters of the contact structure from vertical cylindrical holes to horizontal linear grooves. This parameter change allows the structure to better accommodate varying dielectric layer thicknesses between array and peripheral regions, as the linear configuration can extend across thickness variations more effectively than vertical plugs, thereby reducing manufacturing complexity.
3Productivity
If device size is miniaturized, then integration density increases, but resistance of connecting plugs increases affecting operating current
Solution Approach 1:
By transitioning from point-like vertical plugs to extended linear contact lines, the patent increases the effective contact area without increasing the footprint area. This dimensional extension along the linear direction allows better electrical connection with lower resistance while maintaining high integration density, as the contact line can serve multiple function transistors along its length.
Solution Approach 2:
The array contact line is formed as a preliminary structure before final device assembly, establishing low-resistance electrical pathways in advance. This preliminary action ensures that even as devices are miniaturized, the connecting resistance remains low because the conductive pathways are already optimized and in place, facilitating better current flow for high-density integration.
Data Source
AI summary
The present disclosure provides a method of forming a semiconductor device and a semiconductor device. The method of forming a semiconductor device includes the following steps: providing a base, where the base includes a substrate and an array region located above the substrate, and the array region includes a first semiconductor structure and a first dielectric layer that covers a surface of the first semiconductor structure; forming, in the first dielectric layer, a groove exposing the first semiconductor structure, where the groove runs through the first dielectric layer along a direction parallel to a surface of the substrate; and filling the groove with a conductive material to form an array contact line.