Semiconductor Array Density Optimization via Segmented Sub-arrays

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Solution Overview

Problem

Conventional semiconductor device manufacturing faces yield loss due to stringent layout pattern uniformity requirements, often resulting in late-stage design cycle delays from maximum and minimum density rule violations in unit cell arrays.

Innovation Solution

A method and system that utilize a computing apparatus to define an array of unit cells with density features between sub-arrays, generating density parameters based on unit cell parameters and design limits, employing linear mixed-integer programming to optimize array density and minimize area violations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If unit cells are instantiated into closely-packed sub-arrays to minimize overall array size, then area utilization is improved, but density rule violations occur due to continuous keep-out zones

Engineering Contradiction:

Improvearray sizeVSAvoidpattern uniformity

Core Design Contradiction:

Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent divides the array into multiple sub-arrays with density control features inserted between them. This segmentation allows independent control of density in different regions, enabling the array to meet minimum density requirements while maintaining compact overall size. The keep-out zones are segmented and redistributed across sub-array boundaries rather than forming continuous blocks.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different density characteristics to different regions of the array by inserting density control features (such as dummy transistors or capacitors) specifically in regions where minimum density requirements are not met. This local adjustment allows the array to satisfy density rules without uniformly increasing spacing throughout the entire structure.

Inventive Principle:

Principle #3Local quality

2Manufacturing precision

If density control features are inserted to satisfy minimum density requirements, then manufacturing precision is improved, but array area increases

Engineering Contradiction:

Improvepattern uniformityVSAvoidarray size

Core Design Contradiction:

Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent employs an iterative optimization process that dynamically adjusts the placement and density of control features based on the specific array configuration and density violations detected. The system calculates optimal positions for density control features to minimize area impact while satisfying all density requirements, adapting the solution to the particular layout rather than applying fixed spacing rules.

Inventive Principle:

Principle #15Dynamics

3Adaptability or versatility

If design components occupy large fraction of cell area to maximize functionality, then device capability is improved, but maximum density rule violations occur when instantiated as array

Engineering Contradiction:

Improvedevice functionalityVSAvoiddensity rule compliance

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent introduces density control features as intermediary elements between the functional components and the density requirements. These features (such as dummy transistors or capacitors) act as buffers that help the array meet minimum density requirements without reducing the size or functionality of the actual device components. The control features are strategically placed in keep-out zones or low-density regions to provide the necessary density without interfering with functional operation.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Manufacturing precision

If stringent layout pattern uniformity is enforced to meet density rules, then manufacturing precision is improved, but yield loss occurs due to late-stage design cycle delays

Engineering Contradiction:

Improvedensity rule complianceVSAvoiddesign cycle time

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent performs density analysis and inserts density control features during the preliminary design stage rather than waiting for late-stage DRC checks. The system calculates required density control features based on unit cell parameters and array configuration before final layout completion, allowing designers to address density issues early when modifications are easier and less costly.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS8716869B2Cell array and density features with decoupling capacitors

Publication Date: 2014.05.06 MEDIATEK INC

AI summary

A method includes defining an array including a plurality of unit cells, receiving unit cell density parameters in a computing apparatus, and defining a plurality of sub-arrays of unit cells using the computing apparatus. The computing apparatus defines density features disposed between adjacent sub-arrays. The computing apparatus generates density feature density parameters based on the unit cell density parameters and at least one density limit.