Semiconductor Module Array Layout for Fine-Pitch Alignment
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Solution Overview
Problem
Existing semiconductor packages face limitations in reducing connection electrode pitch, leading to performance differences in interconnect bandwidth and overall device performance, especially when increasing the number of connection terminals, which can be addressed by subdividing semiconductor chips into functional blocks and distributing them in multiple packages.
Innovation Solution
A semiconductor module array device with a substrate design that includes orthogonal alignment regions and metal pads, allowing for high-density mounting of semiconductor modules with alignment chips fixed to metal pads, enabling accurate alignment and reliable electrical connections without sockets, and facilitating easy replacement of failed modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch of connection electrodes is reduced to increase the number of terminals, then the density of connection terminals is improved, but the performance difference in interconnect bandwidth increases and manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent introduces alignment chips as intermediary components between the substrate and semiconductor modules. These alignment chips include alignment electrodes that mediate the positioning process, enabling precise alignment of connection terminals even at reduced pitch. The alignment chips act as a buffer layer that facilitates accurate positioning without requiring direct high-precision alignment between the substrate electrodes and module terminals.
Solution Approach 2:
The patent implements preliminary alignment actions by pre-positioning alignment chips on the substrate before mounting semiconductor modules. The alignment chips are equipped with alignment electrodes that are预先 configured to guide the positioning of subsequent components. This preliminary setup establishes a reference framework that simplifies subsequent alignment operations and maintains precision even with reduced electrode pitch.
2Quantity of substance
If semiconductor chips are subdivided into multiple packages to increase connection terminals, then the quantity of connection terminals is improved, but the device complexity increases
Solution Approach 1:
The patent designs alignment chips with multi-functional capabilities. The alignment chips serve multiple purposes: they provide mechanical alignment references, establish electrical connections through alignment electrodes, and facilitate heat dissipation. By making the alignment chips universal components that perform multiple functions, the patent reduces overall device complexity despite increasing the number of connection terminals through chip subdivision.
Solution Approach 2:
The patent segments semiconductor functionality into multiple modular packages, each containing semiconductor modules mounted on substrate regions. This segmentation allows independent optimization of each module while maintaining overall system functionality. The modular structure with standardized alignment chips enables scalable configuration, reducing the complexity burden by creating reusable, standardized components.
3Manufacturing precision
If alignment chips are positioned at different distances in orthogonal directions, then the alignment precision is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent employs asymmetric positioning of alignment chips, where the distances between alignment chips in orthogonal directions are intentionally made different. This asymmetric configuration optimizes alignment precision for specific mounting directions and module geometries. The asymmetry is designed into the alignment chip layout to match the actual alignment requirements of semiconductor modules, providing superior positioning accuracy in critical directions.
Solution Approach 2:
The patent applies different alignment chip positioning strategies for different regions and directions. Instead of uniform spacing, the alignment chips are positioned with locally optimized distances tailored to specific alignment requirements. This local quality approach allows precise alignment in critical areas while maintaining reasonable manufacturing complexity by only applying asymmetric positioning where genuinely needed.
Data Source
AI summary
A distance between outermost parts of alignment chips in a direction normal to a surface of a substrate is different between a first direction and a second direction along terminal placement surfaces. The plurality of alignment chips include a first alignment chip fixed to a first metal pad, and a second alignment chip fixed to a second metal pad. The first alignment chip and the second alignment chip are oriented in different directions on the surface of the substrate. A semiconductor module includes a first side surface part extending in the second direction and facing the first alignment chip, and a groove part formed in a portion of the first side surface part. A portion of the second alignment chip is positioned in the groove part.