Semiconductor Assembly Array Moulding for Low-Resistance Singulation

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Solution Overview

Problem

Existing semiconductor assembly manufacturing methods face challenges in reducing component resistance while maintaining a compact footprint and improving manufacturing efficiency, as the size of the die is limited by the die paddle area and current methods are inefficient in material usage and prone to damage during singulation.

Innovation Solution

A method involving a lead frame with die paddles arranged in a 2 x n array, where a fused casing is molded over multiple semiconductor assemblies, cut at three positions, and a lead side is punched to singulate individual assemblies, allowing for a larger die size, reduced material waste, and improved reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the size of the die is increased to reduce component resistance, then component resistance decreases, but the area available on the die paddle is exceeded

Engineering Contradiction:
Improvecomponent resistanceVSAvoiddie paddle area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from individual die paddle assembly to a multi-die array configuration (2x2, 2x3, or 3x3 arrays). By arranging multiple dies in a two-dimensional array on the die paddle, the effective functional area is increased without exceeding the physical boundaries of a single die paddle, thereby reducing component resistance while maintaining area constraints.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple semiconductor dies are combined into a single array assembly on one die paddle. The dies are electrically connected through the lead frame structure, merging their functions into a unified component that achieves lower resistance by parallel conduction paths while utilizing the die paddle area more efficiently.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If traditional individual moulding and punching methods are used, then manufacturing simplicity is maintained, but manufacturing efficiency decreases and material wastage increases

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidmaterial wastage
Core Design Contradiction:
ProductivityVSLoss of substance

Solution Approach 1:

Multiple semiconductor assemblies are moulded together in a single injection moulding process to form a fused casing that encapsulates the entire die array. This consolidated moulding approach eliminates the need for multiple individual moulding operations, significantly improving manufacturing efficiency and reducing material wastage by minimizing redundant gating and runner systems.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The fused casing is moulded in advance to encapsulate the complete die array before any cutting or separation operations. This preliminary encapsulation protects the dies and lead frame structure, enabling subsequent precise cutting operations with reduced material loss and improved manufacturing efficiency.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If traditional punching methods are used for singulation, then process simplicity is maintained, but the risk of damage during singulation increases

Engineering Contradiction:
Improverisk of damage during singulationVSAvoidsingulation process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The fused casing is cut into segments at predetermined locations to separate individual semiconductor assemblies. This segmentation approach allows controlled separation through cutting operations that follow the encapsulated structure, reducing the risk of damage compared to traditional punching methods that apply concentrated mechanical force.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The fused casing acts as an intermediary protective structure that encloses the fragile semiconductor components during the singulation process. By cutting the resilient fused casing material rather than directly applying force to the enclosed components, the risk of damage is significantly reduced while maintaining process control.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Area of stationary object

If die paddles are arranged in non-opposing configuration, then manufacturing simplicity is maintained, but die paddle density decreases

Engineering Contradiction:
Improvedie paddle densityVSAvoidarray configuration complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The die array is configured with opposing orientations where adjacent die paddles are arranged asymmetrically to maximize space utilization. This asymmetric opposing configuration allows denser packing of dies on the lead frame while maintaining electrical connectivity through the lead frame structure, increasing die paddle density without excessive complexity.

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces component resistance by up to 20%, increases die paddle density, and enhances manufacturing efficiency by minimizing material wastage and risk of damage during singulation, while maintaining a compact assembly footprint.

Implementation Method 1

moulding a fused casing over the plurality of semiconductor assemblies using a mould which surrounds the 2 x n array

Methodology Applied
Scientific EffectMoulding:

Implementation Method 2

cutting the fused casing at at least three positions, partially surrounding an individual one of the plurality of semiconductor assemblies

Methodology Applied
Scientific EffectCutting:

Implementation Method 3

punching a lead side of the semiconductor assembly, to define an individual casing, from the fused casing

Methodology Applied
Scientific EffectPunching:

Data Source

PatentEP4485510A1A method of manufacturing semiconductor assemblies
Publication Date: 2025.01.01 NEXPERIA BV
  • EP4485510A1 patent drawingFigure 1~2
  • EP4485510A1 patent drawingFigure 3~5
  • EP4485510A1 patent drawingFigure 6~8

AI summary

There is disclosed a method of manufacturing a batch of semiconductor assemblies. The method comprises coupling a plurality of dies to a plurality of die paddles, the plurality of die paddles being provided on a lead frame in a 2 x n array in pairs having an opposing orientation. Each die paddle defines a respective semiconductor assembly. The method further comprises coupling a plurality of connectors to the plurality of dies. The method further comprises moulding a fused casing over the plurality of semiconductor assemblies using a mould which surrounds the 2 x n array, the fused casing at least partly surrounding the 2 x n array. The method further comprises cutting the fused casing at at least three positions, partially surrounding an individual one of the plurality of semiconductor assemblies, and punching a lead side of the semiconductor assembly, to define an individual casing, from the fused casing, and singulate the semiconductor assembly from the 2 x n array.