Semiconductor Assembly Layout With Fused Casing Singulation
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Solution Overview
Problem
Existing semiconductor assembly manufacturing methods face challenges in reducing component resistance while maintaining a compact footprint and improving manufacturing efficiency, as the size of the die is limited by the die paddle area, and existing methods are inefficient in terms of material usage and singulation processes.
Innovation Solution
A method involving a 2×n array of die paddles with opposing orientation, where dies are coupled to die paddles, connectors are added, and a fused casing is molded over the array, cut at three positions to singulate individual semiconductor assemblies, reducing material waste and allowing for a larger die size, thereby decreasing component resistance and increasing manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the size of the die is increased to reduce component resistance, then component resistance decreases, but the area available on the die paddle is exceeded
Solution Approach 1:
The patent merges multiple die paddles (at least two) into a single semiconductor assembly, allowing the combined die area to exceed the area of a single die paddle while maintaining compatibility with existing packaging footprints. This merging enables larger effective die area for reduced resistance without increasing the overall assembly footprint.
Solution Approach 2:
The patent transitions from a single-die-padde configuration to a multi-die-paddle arrangement, effectively adding a dimensional aspect to the die area utilization. By arranging multiple die paddles in specific configurations (e.g., side-by-side or stacked), the patent achieves larger total die area within the same footprint constraints.
2Productivity
If traditional manufacturing methods are used with individual molding and punching, then each assembly can be processed independently, but manufacturing efficiency is reduced and material wastage increases
Solution Approach 1:
The patent combines multiple semiconductor assemblies into a single fused casing that encapsulates multiple die paddles and their associated components. This merging allows for single-step molding and processing of multiple assemblies simultaneously, dramatically improving manufacturing efficiency and reducing material wastage compared to individual processing of each assembly.
Solution Approach 2:
The fused casing serves multiple functions simultaneously: it encapsulates and protects multiple die paddles, provides structural support for the entire array, and enables collective processing during manufacturing. This multi-functionality allows a single casing structure to handle multiple assemblies, improving productivity and reducing per-unit material consumption.
3Quantity of substance
If die paddles are arranged in opposing pairs in a 2×n array, then die paddle density increases, but the complexity of the array configuration increases
Solution Approach 1:
The patent employs asymmetric arrangement of die paddles in opposing pairs within the 2×n array configuration. By strategically positioning die paddles with different orientations and configurations in opposing pairs, the patent achieves high die paddle density while managing the complexity through systematic asymmetry rather than random arrangement.
Solution Approach 2:
The patent segments the 2×n array into manageable opposing pairs of die paddles, where each pair can be independently configured and processed. This segmentation approach allows for increased overall density while maintaining manageable complexity at the pair level, making the configuration systematic and easier to manufacture despite the high density requirement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces component resistance by up to 20%, increases die paddle density on the lead frame, and improves manufacturing efficiency by reducing material wastage and warping, while also simplifying the singulation process and enhancing reliability.
Implementation Method 1
moulding a fused casing over the plurality of semiconductor assemblies using a mould which surrounds the 2×n array
Implementation Method 2
cutting the fused casing at at least three positions, partially surrounding an individual one of the plurality of semiconductor assemblies
Implementation Method 3
punching a lead side of the semiconductor assembly, to define an individual casing, from the fused casing
Data Source
AI summary
A method of manufacturing a batch of semiconductor assemblies is provided. The method includes coupling dies to die paddles, the die paddles being provided on a lead frame in a 2×n array in pairs having an opposing orientation. Each die paddle defines a respective semiconductor assembly. The method further includes coupling connectors to the dies, and moulding a fused casing over the semiconductor assemblies using a mould which surrounds the 2×n array, the fused casing at least partly surrounding the 2×n array. The method further includes cutting the fused casing at, at least three positions, partially surrounding an individual one of the 10 plurality of semiconductor assemblies, and punching a lead side of the semiconductor assembly, to define an individual casing, from the fused casing, and singulate the semiconductor assembly from the 2×n array.