Semiconductor Assembly Via Vertical Alignment
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Solution Overview
Problem
Existing semiconductor assemblies face challenges in achieving optimal communication between logic ICs and companion ICs due to uneven trace lengths on circuit boards, which can lead to signal delays and routing constraints.
Innovation Solution
A semiconductor assembly design that uses a printed circuit board (PCB) with vertically aligned contacts on the top and bottom surfaces, electrically coupled by vias, ensuring consistent and minimal length connections between integrated circuits, thereby improving communication efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traces are routed on the circuit board to connect logic IC and companion IC, then the ICs can be electrically connected, but the trace lengths become unequal causing signal delays
Solution Approach 1:
The patent transitions from two-dimensional PCB trace routing to three-dimensional vertical stacking with vias. The logic IC and companion IC are positioned on opposite sides of the PCB and connected through vertical vias, changing the connection dimension from planar to spatial, thereby achieving equal and minimal trace lengths.
Solution Approach 2:
The patent merges the connection path by having traces from both ICs terminate at the same via location. The vias serve as a common connection point, combining the signal paths from the logic IC and companion IC into a single vertical connection structure, ensuring equal length and minimal signal delay.
2Speed
If traces are kept short for high-speed communication, then signal quality improves, but routing flexibility is reduced
Solution Approach 1:
By moving connections to the vertical dimension through vias, the patent achieves short trace lengths without constraining horizontal routing flexibility. The vertical via connections are inherently short, while the horizontal trace routing can still be optimized for different signal requirements and IC placements.
Solution Approach 2:
The patent applies different connection qualities to different signal types. Critical high-speed signals use the short via-connected traces, while other signals can use longer PCB traces. This localized optimization allows short traces where needed without compromising overall routing flexibility.
3Reliability
If multiple traces are routed between ICs on a PCB, then electrical connection is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple connection functions into a single via structure. Instead of routing separate traces for each signal through the PCB layers, all connections are established through vertical vias at standardized locations, simplifying the manufacturing process and reducing trace routing complexity.
Solution Approach 2:
The via structures serve multiple functions: they provide electrical connection, mechanical support, and signal routing. This multi-functionality reduces the need for separate manufacturing steps and simplifies the overall PCB fabrication process while maintaining reliable electrical connections.
Data Source
AI summary
A semiconductor assembly with an integrated circuit (IC) and a companion device. An exemplary semiconductor assembly includes a printed circuit board (PCB) and first and second ICs. The PCB has first contacts on a top surface and second contacts on a bottom surface. The first contacts are vertically aligned with the second contacts and are electrically coupled by vias in the PCB. The first IC has first terminals respectively coupled to the first contacts of the PCB, the first terminals including first input/output (IO) terminals. The second IC includes at least one die, and second terminals coupled to at least a portion of the second contacts of the PCB. The second terminals include second IO terminals of the companion die, and are respectively coupled to those of the second contacts that are vertically aligned with those of the first contacts respectively coupled to the first IO terminals.


