Semiconductor Structure Asymmetric Capacitor Array Layout
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Solution Overview
Problem
Capacitors at the edge of the array region in DRAM semiconductor structures are prone to damage due to stress from the peripheral circuit region, leading to reduced storage performance.
Innovation Solution
Virtual lines connecting centers of three consecutively adjacent capacitors at the edge of the array region define a virtual angle greater than 90°, preventing a rectangular pattern and reducing stress on capacitors, thereby minimizing damage during etching and exposure processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple capacitors are arranged in a rectangular array in the array region, then the storage capacity is increased, but the capacitors at the corner and edge of the array are prone to damage due to stress from the peripheral circuit region
Solution Approach 1:
The patent applies asymmetry by changing the capacitor array layout from a rectangular pattern to a triangular pattern. In the triangular array, capacitors are arranged such that virtual lines connecting centers of any three consecutively adjacent capacitors define a virtual angle greater than 90 degrees. This asymmetric triangular configuration eliminates the corner positions that exist in rectangular arrays, thereby distributing stress more evenly and preventing the loading effects that cause capacitor damage at rectangular array corners and edges.
2Ease of manufacture
If capacitors are arranged in a rectangular array, then manufacturing is simplified, but the loading effect during etching and exposure processes causes capacitor damage at edges and corners
Solution Approach 1:
The patent transforms the symmetric rectangular array into an asymmetric triangular array where capacitors are positioned such that virtual lines connecting centers of any three consecutively adjacent capacitors define a virtual angle greater than 90 degrees. This asymmetric triangular configuration eliminates the geometric weaknesses at rectangular corners and edges, distributing mechanical stress uniformly throughout the array during etching and exposure processes, thereby preventing loading effect damage while maintaining manufacturing feasibility.
3Ease of operation
If the array region is surrounded by the peripheral circuit region, then the driving circuit can be connected with each capacitor, but stress from the peripheral circuit region damages the capacitors at the array edge
Solution Approach 1:
The patent applies asymmetry by implementing a triangular capacitor array configuration where virtual lines connecting centers of any three consecutively adjacent capacitors define a virtual angle greater than 90 degrees. This triangular arrangement eliminates the edge and corner positions in rectangular arrays that are most vulnerable to stress from surrounding peripheral circuits. The symmetric triangular geometry distributes stress uniformly from all directions, enhancing capacitor strength and resistance to stress-induced damage while maintaining full connectivity with the peripheral driving circuits.
Data Source
AI summary
The present application provides a semiconductor structure and a manufacturing method thereof, and relates to the field of display technology. The semiconductor structure includes a substrate. The substrate includes an array region and a peripheral circuit region surrounding the array region. Multiple capacitors are arranged in an array in the array region. Virtual lines connecting centers of any three consecutively adjacent capacitors among the multiple capacitors located at an edge of the array region define a virtual angle greater than 90°.