Semiconductor Device Asymmetric Chip Layout Warpage Reduction
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Solution Overview
Problem
Semiconductor devices with multiple chips on a substrate face warpage or deformation issues due to differing thermal expansion coefficients of the substrate, semiconductor chips, resin, and lid, making it difficult to mount them on a wiring substrate, especially when the substrate area increases without thickness, leading to potential solder ball misalignment in BGA configurations.
Innovation Solution
The solution involves mounting two semiconductor chips diagonally on a substrate, with one chip positioned at the intersection of the diagonals, using a hat-type lid less susceptible to warpage, and employing heat dissipation resin and underfill to minimize deformation, while maintaining a thickness ratio between the substrate and lid to reduce overall warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the area of the substrate is increased to accommodate multiple semiconductor chips, then the device functionality is improved, but warpage or deformation is likely to occur due to thermal expansion differences
Solution Approach 1:
The patent positions semiconductor chips asymmetrically on the substrate, specifically placing at least one chip over each of the two centerlines that couple the middle points of opposite sides of the substrate. This asymmetric arrangement balances the thermal expansion forces across the substrate, preventing warpage while accommodating multiple chips for enhanced functionality.
2Stability of the object's composition
If the substrate thickness is increased to prevent warpage, then structural stability is improved, but the process of making through holes becomes more difficult
Solution Approach 1:
The patent maintains the substrate thickness within a specific parameter range (0.5 mm to 2.0 mm) to achieve an optimal balance. This parameter optimization ensures the substrate is thin enough for easy through-hole fabrication while being thick enough to maintain structural stability and resist warpage under thermal stress.
3Ease of manufacture
If the substrate area is increased without increasing thickness, then ease of manufacture is improved, but warpage or deformation is likely to occur during heating or cooling
Solution Approach 1:
The patent employs asymmetric chip positioning on the substrate, with chips arranged along the centerlines rather than in a symmetric grid pattern. This asymmetric configuration distributes thermal stresses more evenly across the large-area thin substrate, preventing deformation during thermal cycling while maintaining ease of manufacture.
Solution Approach 2:
The patent applies different thermal management strategies to different regions of the substrate. By positioning chips specifically along centerlines and using local thermal expansion compensation techniques in critical areas, the patent achieves uniform thermal behavior across the entire large-area substrate without increasing thickness.
4Manufacturing precision
If warpage or deformation occurs in the semiconductor device, then mounting difficulty increases, but solder ball alignment may fail to reach the wiring board
Solution Approach 1:
The asymmetric chip arrangement along substrate centerlines prevents warpage that would cause BGA solder balls to misalign with the wiring board. This positioning strategy ensures that all solder balls maintain proper alignment and reach their corresponding pads during the mounting process.
Solution Approach 2:
The patent preemptively addresses potential warpage issues by designing the chip layout to counteract thermal expansion forces before they can cause deformation. This preliminary design prevents the condition that would lead to solder ball misalignment, ensuring reliable connections from the outset.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement effectively reduces warpage in semiconductor devices, ensuring reliable mounting and preventing solder ball misalignment, with measured warpage minimized to 200 μm or less, significantly improving the device's structural integrity and mounting precision.
Implementation Method 1
the substrate included in the semiconductor device, semiconductor chips, resin for sealing the semiconductor chips on the substrate, and lid for covering the semiconductor chips have different thermal expansion coefficients, so deformation may occur during heating or cooling
Data Source
AI summary
A semiconductor device includes a main surface, a back surface opposite to the main surface, a first side on the main surface, a second side opposite to the first side, a third side between the first side and the second side, a fourth side opposite to the third side, a first point on a periphery of the main surface between the first side and the third side, a second point on the periphery of the main surface between the second side and the fourth side, a third point on the periphery of the main surface between the first side and the fourth side, anda fourth point on the periphery of the main surface between the third side and the second side, a first semiconductor chip disposed over the main surface of the substrate, and a second semiconductor chip disposed over the main surface of the substrate.