Semiconductor Device Warpage Control via Asymmetric Chip Stacking
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Solution Overview
Problem
Semiconductor devices with multiple chips experience warpage and twisting due to thickness differences in sealing resins and wire deformations, making it difficult to achieve small size and thinness while maintaining reliability.
Innovation Solution
A semiconductor device configuration with a third semiconductor chip straddling two lower chips, using a thicker adhesive layer to embed wires and fill the space between chips with a sealing material, which reduces warpage and prevents voids around wires, enhancing the device's symmetry and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips are planarly assembled on a wiring substrate, then the device achieves small size and thinness, but warpage and twisting occur due to thickness differences in sealing resins
Solution Approach 1:
The patent applies asymmetry by strategically placing a third semiconductor chip to straddle the boundary between two stacked chip groups. This asymmetric positioning creates a counterbalancing effect that compensates for the warpage caused by unequal sealing resin thicknesses, transforming the instability into a controlled structural feature
Solution Approach 2:
The third semiconductor chip functions as a counterweight element. By positioning it asymmetrically across the boundary of the two stacked chip groups, it provides a balancing effect that offsets the warpage forces generated by the thickness difference in sealing resins, thereby stabilizing the overall device structure
2Stability of the object's composition
If a third semiconductor chip is added to straddle two stacked chips, then warpage is suppressed and symmetry is improved, but the device complexity increases
Solution Approach 1:
The third semiconductor chip serves multiple functions simultaneously: it acts as a functional semiconductor component, provides structural balancing to suppress warpage, and enhances the overall symmetry of the device. This multi-functionality justifies the added complexity by delivering multiple benefits from a single structural element
3Length of stationary object
If sealing resin thickness is reduced for thinner devices, then device thinness is achieved, but wire deformation and voids occur
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration with asymmetric positioning. By utilizing the vertical dimension and asymmetric spatial arrangement, it achieves thinness while maintaining adequate sealing resin thickness to prevent wire deformation and void formation
Data Source
AI summary
A semiconductor device comprises a wiring substrate, first and second semiconductor chips mounted on the wiring substrate so as to be spaced apart from each other, a third semiconductor chip mounted on the first and second semiconductor chips, first and second adhesive layers that are provided between the first and second semiconductor chips and the wiring substrate so as to bond the first and second semiconductor chips to the wiring substrate, and a third adhesive layer that is provided between the third semiconductor chip and the first and second semiconductor chips so as to bond the third semiconductor chip to the first and second semiconductor chips, with its thickness being made thicker than that of the first and second adhesive layers, a sealing layer covering the wiring substrate, and a filling layer that is provided between the first and second semiconductor chips and is different from the sealing layer.