Semiconductor Contact Layout With Asymmetric Separation Structure

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Solution Overview

Problem

The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices requires finer patterns and three-dimensional channel structures, such as FinFETs, to overcome limitations in planar metal oxide semiconductor FETs, but existing technologies face challenges in achieving optimal integration density and electrical properties.

Innovation Solution

A semiconductor device design featuring active patterns on a substrate with asymmetrical and symmetrical separation structures between source/drain contacts, where the upper surface of one source/drain contact is higher than the other, and a separation structure with varying surface levels to enhance electrical properties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If integration density is increased to achieve high performance and high speed, then productivity and functionality improve, but manufacturing precision and pattern formation difficulty worsen

Engineering Contradiction:
Improveintegration densityVSAvoidpattern formation precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The device is divided into multiple active patterns (first active pattern, second active pattern) with separate source/drain regions and contacts. This segmentation allows independent optimization of each pattern while achieving high overall integration density, resolving the contradiction between productivity and manufacturing precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first and second source/drain contacts are formed at different heights, creating an asymmetrical structure. The first source/drain contact has a higher upper surface than the second source/drain contact, allowing optimized electrical connections for different transistor types (e.g., NFET and PFET) while maintaining compact integration.

Inventive Principle:
Principle #4Asymmetry

2Ease of manufacture

If planar metal oxide semiconductor FET structure is used, then manufacturing is simpler, but operating characteristics and performance are limited

Engineering Contradiction:
Improvestructure simplicityVSAvoidoperating characteristics
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The invention transitions from a planar structure to a three-dimensional structure by forming source/drain contacts at different heights. The first source/drain contact extends to a first height and the second source/drain contact extends to a second height, enabling vertical stacking and improved electrical characteristics while maintaining manufacturability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If source/drain contacts are formed at the same level, then manufacturing is easier, but electrical properties and device performance are suboptimal

Engineering Contradiction:
Improvecontact formation simplicityVSAvoidelectrical properties
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The first source/drain contact and second source/drain contact are deliberately formed at different heights to optimize electrical properties. The first source/drain contact has a higher upper surface than the second source/drain contact, allowing tailored electrical connections for different transistor types and improved overall device performance.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

Different regions of the device have different contact heights optimized for their specific functions. The first source/drain contact region is optimized for one transistor type while the second source/drain contact region is optimized for another transistor type, allowing each region to have the quality needed for its specific purpose.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240096980A1Semiconductor device
Publication Date: 2024.03.21 SAMSUNG ELECTRONICS CO LTD
  • US20240096980A1 patent drawing
  • US20240096980A1 patent drawing
  • US20240096980A1 patent drawing

AI summary

A semiconductor device includes an active pattern on a substrate with first and second regions; first and second source/drain regions on the first and second regions; first and second source/drain contacts on the first and second source/drain regions; and a separation structure intersecting the active pattern between the first and second source/drain contacts, and extending into the active pattern between the first and second source/drain regions, wherein an upper surface of the second source/drain contact is higher than an upper surface of the first source/drain contact, and wherein the separation structure has an asymmetrical structure having an upper surface of a first portion adjacent to the first source/drain contact higher than an upper surface of a second portion adjacent to the second source/drain contact.