Semiconductor Device Asymmetric Contact Plug for Reduced Chip Size
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to reduce chip size while maintaining or improving performance, particularly when bonding multiple devices, as existing electrode structures hinder the reduction of electrode pitch on the rear surface due to alignment and flatness issues, leading to increased wiring delays and resistance losses.
Innovation Solution
The semiconductor device employs a configuration where the contact plug width is narrower than the electrode width, allowing for direct bonding of layers with a specific conductive layer structure, including a barrier metal film, to reduce chip size and improve performance by minimizing electrode pitch and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional electrode structures are used with equal contact plug and electrode widths, then alignment is easier, but the electrode pitch cannot be reduced and chip size cannot be reduced
Solution Approach 1:
The patent applies asymmetry by making the contact plug width narrower than the electrode width. This asymmetric configuration allows the contact plug to be positioned within the electrode area, enabling reduced electrode pitch while maintaining alignment feasibility. The narrower contact plug fits within the broader electrode footprint, resolving the contradiction between reducing chip size and maintaining alignment precision.
2Area of stationary object
If electrode pitch is reduced to reduce chip size, then chip area decreases, but wiring delays and resistance losses increase
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration. By bonding semiconductor wafers in multiple layers and forming vertical conductive paths through contact plugs, the design reduces horizontal electrode pitch while maintaining electrical performance through vertical connectivity. This dimensional change allows compact chip area without sacrificing wiring performance.
3Area of stationary object
If contact plug width is made narrower than electrode width, then electrode pitch can be reduced and chip size reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the sacrificial layer in advance during wafer fabrication, before bonding. This sacrificial layer defines the contact plug formation area and is removed after bonding to create the contact plug. By preparing this structure beforehand, the complex multi-step process of forming narrower contact plugs within broader electrodes is simplified and integrated into the existing manufacturing flow.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first semiconductor circuit layer including a first conductive layer, a second semiconductor circuit layer including a second conductive layer, and a third semiconductor circuit layer between the first semiconductor circuit layer and the second semiconductor circuit layer, the third semiconductor circuit layer including a third conductive layer in contact with the first conductive layer, a fourth conductive layer in contact with the second conductive layer, and a fifth conductive layer in contact with the third conductive layer and electrically connected to the fourth conductive layer. The fifth conductive layer has a width that is narrower than a width of the third conductive layer.