Semiconductor Element Asymmetric Extraction Gate Charge Transfer
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Solution Overview
Problem
Conventional solid-state imaging devices with lock-in pixels face challenges in charge transfer efficiency due to potential gradient issues, leading to incomplete charge transfer and structural complexity.
Innovation Solution
A semiconductor element design where the extraction-gate electrode is placed on only one side of the light-receiving surface-buried region, controlling the potential gradient across the charge-transferring route to ensure efficient charge transfer without a gate structure between the light-receiving and accumulation regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate structure of MOS transistor is used for charge transfer, then charge transfer control is achieved, but electrons are captured in traps at the boundary between silicon and silicon oxide film causing transfer delay and incomplete transfer
Solution Approach 1:
The patent removes the gate structure (insulation film and gate electrode) from between the light-receiving region and accumulation region, eliminating the source of electron traps at Si-SiO2 boundaries. This extraction of the problematic component directly resolves the electron capture issue and transfer delay problem while maintaining charge transfer control through alternative potential gradient mechanisms.
Solution Approach 2:
The patent introduces a potential gradient control mechanism using the extraction-gate electrode positioned at the side of the light-receiving region. This mediator controls the charge transfer path through electrostatic potential distribution without requiring direct contact between charges and the gate insulation film, thereby avoiding trap capture while maintaining transfer control.
2Reliability
If extraction-gate electrodes are arranged on both sides of the light-receiving surface-buried region, then charge transfer control is improved, but the structure becomes complex
Solution Approach 1:
The patent employs an asymmetric arrangement where the extraction-gate electrode is positioned only on one side of the light-receiving surface-buried region rather than symmetrically on both sides. This asymmetric configuration maintains effective charge transfer control through the potential gradient while significantly reducing structural complexity and the number of components required.
Solution Approach 2:
The single extraction-gate electrode performs multiple functions: it controls the potential gradient for charge transfer, modulates the charge transfer timing, and eliminates the need for separate gate structures. This multi-functionality reduces overall device complexity while maintaining transfer control effectiveness.
3Ease of operation
If a gate insulation film is used between light-receiving and accumulation regions, then charge transfer is controlled, but electrons are captured in traps at the silicon-silicon oxide boundary
Solution Approach 1:
The patent completely removes the gate insulation film from the charge transfer path between the light-receiving region and accumulation region. By extracting this problematic insulating layer, electrons can transfer directly through the silicon medium without encountering trap sites at Si-SiO2 boundaries, thereby eliminating the fundamental cause of transfer inefficiency.
Solution Approach 2:
The patent replaces the mechanical/gate-based control system (insulation film with gate electrode) with an electrostatic field-based control system. The extraction-gate electrode positioned at the side creates a potential gradient that controls charge transfer through electric field effects rather than through direct gate modulation, avoiding contact with trap-prone interfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances charge transfer efficiency, simplifies the pixel structure, and enables high-resolution and high-speed operation by maintaining a non-zero potential gradient across the charge-transferring path, reducing image lag and noise.
Implementation Method 1
the gate insulation film and the extraction-gate electrode on the gate insulation film control the potential of a channel formed in the upper portion of the semiconductor region between the light-receiving surface-buried region and the first extracting-drain region, and the potential of a channel formed in the upper portion of the semiconductor region between the light-receiving surface-buried region and the second extracting-drain region
Implementation Method 2
a light-receiving surface-buried region of n-type to which light is entered; electrons generated by the light-receiving surface-buried region
Data Source
Figure 1
Figure 2
Figure 3(a)~3(c)
AI summary
A solid-state imaging device, in which the transfer efficiency of charges is good, and the structure of the pixel is simple, and a high resolution and a high-speed operation are possible is disclosed, which encompasses a semiconductor region (21) of p-type; a buried region (23) of n-type, configured to serve as a photodiode together with the semiconductor region (21); a extraction region of n-type, configured to extract charges generated by the photodiode from the buried region (23), having higher impurity concentration than the buried region (23); a read-out region (28) of n-type, configured to accumulate charges, which are transferred from the buried region (23) having higher impurity concentration than the buried region (23); and a potential gradient changing means (31, 32), configured to control a potential of the channel, and to change a potential gradient of a potential profile from the buried region (23) to the read-out region (28) and a potential gradient of a potential profile from the buried region (23) to the extraction region, so as to control the transferring/ extraction of charges.