Semiconductor Package With Asymmetric Redistribution Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor integration technologies face challenges in efficiently processing large volumes of data due to limitations in single semiconductor chip functionality, necessitating the development of semiconductor packages with multiple vertically stacked chips for enhanced performance.
Innovation Solution
A semiconductor package design featuring a substrate with a sub semiconductor package, including a sub semiconductor chip, redistribution conductive layers, interconnectors, and a capacitor, which allows for efficient signal and power distribution between main and sub semiconductor chips, facilitating stable power supply and reduced signal transmission distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are vertically stacked to increase integration capacity, then data processing capability is improved, but power supply stability deteriorates due to increased impedance and inductance in power paths
Solution Approach 1:
The patent transitions from planar power distribution to three-dimensional vertical stacking, enabling multiple chips to be arranged in the vertical dimension. This dimensional change allows power and signal interconnectors to be integrated within the stacked structure, reducing power path lengths and improving power supply stability despite the increased complexity of multi-chip integration.
Solution Approach 2:
The patent implements a nested structure where power and signal interconnectors are embedded within the stacked chip architecture. The interconnectors are positioned between chips in the vertical stack, creating a compact nested arrangement that reduces the overall package size while maintaining stable power delivery paths through the multi-chip structure.
2Adaptability or versatility
If signal transmission paths are extended to connect multiple chips, then connectivity is improved, but signal transmission quality deteriorates due to increased impedance and inductance
Solution Approach 1:
The patent utilizes vertical stacking to reduce the horizontal distance between chips, thereby shortening signal transmission paths. By arranging chips in the vertical dimension rather than spreading them out horizontally, the signal paths become more compact, reducing impedance and inductance while maintaining full connectivity between all chips in the stack.
Solution Approach 2:
The patent introduces dedicated power and signal interconnectors as intermediary elements between chips. These interconnectors are specifically designed to mediate the electrical connections, providing low-impedance pathways for signal transmission and power delivery, thereby maintaining signal quality across the multi-chip interface.
3Area of stationary object
If power redistribution conductive layers extend to the edge of the molding layer, then power distribution coverage is improved, but device complexity increases
Solution Approach 1:
The patent applies different extension lengths to power and signal redistribution conductive layers based on their specific requirements. Power redistribution layers extend to the edge of the molding layer to maximize power distribution coverage, while signal redistribution layers have shorter extensions. This localized differentiation optimizes each layer's function without unnecessarily increasing overall device complexity.
Solution Approach 2:
The patent employs asymmetric design where power redistribution conductive layers and signal redistribution conductive layers have different geometries and extension lengths. The power layers extend further to reach the molding layer edge for comprehensive power delivery, while signal layers are more compact. This asymmetric arrangement efficiently addresses the different functional requirements of power and signal distribution.
Data Source
AI summary
A semiconductor package includes a substrate and a sub semiconductor package disposed over the substrate. The sub semiconductor package includes a sub semiconductor chip which has chip pads on its active surface facing the substrate, a sub molding layer which surrounds side surfaces of the sub semiconductor chip and has one surface facing the substrate, and redistribution conductive layers which are connected to the chip pads and extend over the one surface of the sub molding layer. The redistribution conductive layers include a signal redistribution conductive layer, which extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion, and a power redistribution conductive layer, which has a length shorter than a length of the signal redistribution conductive layer and has a power redistribution pad on its end portion.