Semiconductor Interface Chip Asymmetric Layout for Wiring Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In chip-on-chip semiconductor devices, the dense packing of wiring lines on the package substrate leads to congestion and difficulty in connecting vias to electrode pads, making it challenging to route wiring lines efficiently.
Innovation Solution
The configuration of the semiconductor device is modified such that the interface chip is longer in the Y-direction than the core chip, allowing wiring lines to extend in the X-direction, reducing density and facilitating easier routing without congestion, with at least one external electrode disposed outside the core chip's end portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the IF chip is made smaller to reduce circuit surface area, then the chip size is reduced, but the wiring line density increases and routing becomes difficult
Solution Approach 1:
The patent extends the IF chip in the Y-direction (length) while keeping the X-direction width compact, changing the dimensional distribution of the chip. This allows wiring lines to route in the X-direction with lower density, solving the routing difficulty caused by small chip size.
Solution Approach 2:
The IF chip is designed with asymmetric dimensions where the length in the Y-direction is greater than the width in the X-direction. This asymmetric configuration optimizes the wiring space by allowing horizontal routing with reduced density while maintaining compact vertical footprint.
2Adaptability or versatility
If external terminals are positioned according to standard specifications, then compatibility is maintained, but wiring lines become congested and difficult to route
Solution Approach 1:
The patent positions external terminals and electrode pads at specific locations on the package substrate that are optimized for wiring routing. By carefully selecting the locations of external terminals relative to the IF chip boundaries, the design creates local regions with adequate wiring space while maintaining overall standard compatibility.
3Quantity of substance
If wiring lines are densely packed to connect external terminals to IF chip, then connection density is improved, but routing becomes congested and manufacturing difficulty increases
Solution Approach 1:
The extended Y-direction length of the IF chip provides additional spatial dimension for distributing wiring connections. Instead of concentrating all wiring routes in a compact area, the extended dimension allows wiring lines to be spread out, reducing density and manufacturing difficulty while maintaining the required number of connections.
Data Source
AI summary
A semiconductor device includes a package substrate, an IF chip, and a core chip. The package substrate has: first electrodes aligned and disposed on a first rear surface; second electrodes aligned and disposed in the first direction (Y direction) on a first front surface; and wiring that electrically connects the first electrodes and the second electrodes. The IF chip has third electrodes bonded to the second electrodes. The core chip is connected to the IF chip. In the first direction, the length of the IF chip is more than that of the core chip but equal to or less than that of the package substrate. One of the first electrodes is disposed further toward the outside than a core chip end portion in the first direction. At least one of the second electrodes is disposed further toward the outside than the core chip end portion in the first direction.