Semiconductor Device with Asymmetric Source Stress for Mobility
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Solution Overview
Problem
Semiconductor devices face challenges in increasing operation speed and packing density due to high leakage current and reduced channel conductivity, particularly as gate scaling down and channel length shorten, with stress memorization techniques often increasing leakage current.
Innovation Solution
A semiconductor device is manufactured with a recrystallized region having a stacking fault defect on one side of the gate pattern, enhancing carrier mobility by applying asymmetric stress from the source region, while the drain region is formed without a stacking fault defect to reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If stress memorization technique is used to induce stress to channel region, then carrier mobility is improved, but leakage current increases
Solution Approach 1:
The patent applies stress memorization technique selectively only to the source region rather than the entire channel, creating local quality difference. The source region has modified crystal orientation to induce compressive stress for carrier mobility enhancement, while the drain region maintains original structure to avoid leakage current increase. This localized application resolves the contradiction by providing stress benefit only where needed for mobility without the harmful side effect in the drain region.
Solution Approach 2:
The patent creates asymmetric stress distribution by applying stress memorization technique only to the source region and not the drain region. This asymmetry is achieved through selective ion implantation and thermal processing steps that modify only the source region's crystal structure. The asymmetric approach allows the source region to provide stress-induced mobility enhancement while the drain region remains free from stress-related leakage current problems.
2Productivity
If gate is scaled down and channel length is shortened to increase packing density, then device integration is improved, but channel conductivity is reduced
Solution Approach 1:
The patent changes the physical parameters of the source region by modifying its crystal orientation through selective ion implantation and thermal processing. This parameter change induces compressive stress in the source region, which enhances carrier mobility and compensates for the reduced channel conductivity caused by shorter channel length. The parameter change in source region stress state directly addresses the conductivity issue while maintaining the scaled-down gate structure for high packing density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances carrier mobility and reduces leakage current, improving channel conductivity and overcoming short channel effects, thereby increasing the performance of semiconductor devices.
Implementation Method 1
forming an amorphous region by implanting impurities into the substrate, removing the mask, and forming a recrystallized region by forming a stress liner on the substrate to cover the gate pattern and crystallizing the amorphous region
Implementation Method 2
induce compressive stress to a channel region to thereby increase hole mobility in the channel, while inducing tensile stress to the channel region to improve electron mobility in the channel region
Data Source
AI summary
A semiconductor device is formed with a gate pattern formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate at one side of the gate pattern. The semiconductor device can have a reduced leakage current and improved channel conductivity.