Semiconductor Package Asymmetric Chip Stacking Underfill
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Solution Overview
Problem
The challenge lies in stacking semiconductor chips with different widths, as the increased miniaturization of mobile devices and data storage needs require multi-chip semiconductor packages, where the width of upper chips can be greater than lower chips, making it difficult to align and stack them effectively.
Innovation Solution
The solution involves a semiconductor package design where a first semiconductor chip with a smaller width is mounted on a substrate, and a second semiconductor chip with a larger width is stacked on top, using an inclined first under filler to cover the side surface of the first chip and a second under filler to fill the space between the chips and the substrate, allowing for secure and aligned stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips with different widths are vertically stacked to increase storage capacity and reduce device size, then the data storage capability and miniaturization are improved, but the alignment and stacking difficulty increases when upper chips have greater width than lower chips
Solution Approach 1:
An underfiller material is introduced as an intermediary substance between the first and second semiconductor chips. This underfiller fills the width difference gap between chips of different dimensions, enabling proper alignment and stable stacking while maintaining electrical connections and mechanical support throughout the multi-chip structure
Solution Approach 2:
The patent employs asymmetric chip stacking where chips of different widths are deliberately arranged in vertical layers. The underfiller material is applied asymmetrically to compensate for the width mismatch, allowing the structure to accommodate non-uniform chip dimensions while maintaining overall structural integrity
2Adaptability or versatility
If the width of upper semiconductor chips is made greater than lower chips to meet functional requirements, then the functionality and performance are improved, but the stacking alignment becomes difficult
Solution Approach 1:
The underfiller serves as a mediator that bridges the dimensional mismatch between chips of different widths. It is applied to the broader chip to provide an extended bonding surface area, ensuring precise alignment and stable mechanical bonding between chips with asymmetric width dimensions
3Volume of moving object
If semiconductor chips are miniaturized to reduce mobile device size, then the device compactness is improved, but the stacking complexity increases when chips have different widths
Solution Approach 1:
The multi-chip package is segmented into multiple functional layers with chips of different widths stacked vertically. The underfiller material segments the width difference between layers, allowing each chip to maintain its optimized dimensions while achieving compact overall package size through vertical integration
Solution Approach 2:
The patent transitions from horizontal chip arrangement to vertical stacking in the third dimension. By utilizing the vertical dimension for multi-chip integration and employing underfiller to manage width variations, the design achieves compact footprint while accommodating chips of different dimensions through dimensional reconfiguration
Data Source
AI summary
Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface.