Semiconductor Arrangement Asymmetrical Dopant Distribution Single CMOS Process
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges in efficiently forming transistors with different operating voltages within a single CMOS process, leading to asymmetrical dopant distribution around gate structures, which affects the transistor's characteristic curve when forward or reverse biased.
Innovation Solution
The method involves forming a semiconductor arrangement with distinct gate structures and dopant implants for low and high voltage transistors, using specific photoresist patterns and implantation techniques to create asymmetrical shallow wells and pocket implants under the gate structures, allowing for a single CMOS process without additional masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single CMOS process is used to form transistors with different operating voltages, then manufacturing efficiency is improved, but asymmetrical dopant distribution around gate structures occurs affecting transistor characteristic curves
Solution Approach 1:
The patent applies local quality by creating different dopant implantation conditions for different transistor regions. First and second photoresist patterns are formed with different geometries (first photoresist with first geometry, second photoresist with second geometry) to enable selective dopant implantation. This allows low voltage transistors to receive different dopant treatments than high voltage transistors, optimizing each region's electrical characteristics while using a single CMOS process.
Solution Approach 2:
The patent segments the fabrication process by dividing the substrate into different transistor regions (first transistor region and second transistor region) with distinct photoresist patterns. This segmentation enables independent dopant implantation control for low voltage and high voltage transistor regions, resolving the asymmetrical dopant distribution issue while maintaining single CMOS process efficiency.
2Manufacturing precision
If additional masks are used to create asymmetrical dopant distribution, then transistor characteristic curves are improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent achieves multi-functionality by using a single photoresist material and single dopant implantation process to serve multiple purposes: defining both low voltage and high voltage transistor regions, creating asymmetrical dopant distribution, and optimizing characteristic curves for different transistor types. This eliminates the need for additional masks and complex fabrication steps while achieving precise transistor characteristics.
Solution Approach 2:
The patent changes geometric parameters of photoresist patterns (first geometry vs. second geometry) to achieve different dopant implantation outcomes. By varying photoresist geometry rather than adding process steps, the patent creates the necessary asymmetrical dopant distribution for optimized transistor characteristic curves without increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of transistors with varying voltage ratings within a single CMOS process, resulting in improved transistor performance by altering the characteristic curve based on biasing conditions.
Implementation Method 1
a first ion implantation is performed at a first angle to a surface of the substrate to introduce a first dopant into the channel region of the first transistor
Implementation Method 2
a first anneal is performed to redistribute the first dopant under the first gate structure
Data Source
AI summary
A semiconductor arrangement and method of formation are provided. A method of semiconductor formation includes using a single photoresist to mask off an area where low voltage devices are to be formed as well as gate structures of high voltage devices while performing high energy implants for the high voltage devices. Another method of semiconductor fabrication includes performing high energy implants for high voltage devices through a patterned photoresist where the photoresist is patterned prior to forming gate structures for high voltage devices and prior to forming gate structures for low voltage devices. After the high energy implants are performed, subsequent processing is performed to form high voltage devices and low voltage devices. High voltage device and low voltage devices are thus formed in a CMOS process without need for additional masks.