Semiconductor Auto-Precharge Circuit Using Shared Command Address Pins
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Solution Overview
Problem
Semiconductor devices with DDR SDRAM perform data read and write operations but face inefficiencies in auto-precharge operations due to the need for complex address serialization and parallelization, leading to increased circuit complexity and area requirements.
Innovation Solution
A semiconductor device and system that serialize addresses based on input command time, generating internal addresses by parallelizing them using shifting clocks and flag signals to perform write and read auto-precharge operations, reducing the number of flip-flops needed for address latching and shifting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If addresses are serialized and parallelized using traditional methods for auto-precharge operations, then the auto-precharge function can be performed, but the circuit complexity and area requirements increase
Solution Approach 1:
The command address pins are designed to serve multiple functions: they can input both command signals and address signals depending on the timing of the input relative to the clock edge. This eliminates the need for separate dedicated address pins and complex address latching circuits, thereby reducing circuit complexity while maintaining full auto-precharge functionality
Solution Approach 2:
The system uses its own clock signal and existing command address pins to perform address serialization and parallelization without requiring external assistance or additional dedicated address input circuits. The command address pins automatically serve as both command and address input interfaces based on timing, making the system self-sufficient and reducing overall circuit complexity
2Adaptability or versatility
If addresses are serialized and parallelized using traditional methods for auto-precharge operations, then the auto-precharge function can be performed, but the circuit area increases
Solution Approach 1:
The command address pins perform dual duty as both command input and address input interfaces. By timing the address input to occur before the active clock edge and the command input to occur after, the same physical pins are reused for both functions, eliminating the need for separate address pins and reducing the overall circuit area
Solution Approach 2:
The address input circuit and command input circuit are merged into a single shared interface using the command address pins. The timing-based multiplexing combines what would traditionally be separate dedicated circuits into one unified structure, thereby minimizing the circuit area required for auto-precharge operations
3Area of stationary object
If the number of flip-flops is reduced for address latching and shifting, then the circuit area is minimized, but the address serialization and parallelization must be simplified
Solution Approach 1:
The address serialization and parallelization functions are extracted from complex multi-cycle flip-flop-based circuits and implemented using simple single-cycle logic circuits. By removing the need for multi-cycle latching and shifting operations, the patent uses basic logic gates and combinational logic to achieve the same address processing function with significantly reduced complexity
Solution Approach 2:
Instead of using expensive and complex multi-cycle flip-flop structures for address latching and shifting, the patent employs simple, inexpensive single-cycle logic circuits that perform the same function in one clock cycle. This approach sacrifices the reusability of multi-cycle latching but gains significant simplicity and area efficiency
Data Source
AI summary
A semiconductor system includes a controller configured to output a clock, a command and an address; and a semiconductor device configured to generate a flag signal by detecting an input time of the command, which is input in synchronization with the clock in a write auto-precharge operation based on the command, and configured to generate an internal address for performing the write auto-precharge operation, by serializing the address and then parallelizing the flag signal and the serialized address.