Semiconductor Device Back-Gate Potential Retention

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Solution Overview

Problem

The challenge is to create a semiconductor device with favorable electrical characteristics, enabling miniaturization, high integration, high productivity, long-term data retention, high-speed data writing, low power consumption, and design flexibility while avoiding the increase in manufacturing steps that typically decrease yield and productivity.

Innovation Solution

The semiconductor device incorporates transistors with different electrical characteristics formed using semiconductor materials with varying electron affinities, where a first transistor with a specific threshold voltage is used for data writing and retention, and a second transistor with a higher threshold voltage is used to supply a potential to the back gate of the first transistor, allowing for efficient data retention and flexible circuit design without significantly increasing manufacturing steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If transistors with different electrical characteristics are separately manufactured, then design flexibility and electrical characteristics are improved, but the number of manufacturing steps increases drastically, leading to decreased yield and productivity

Engineering Contradiction:
Improvedesign flexibilityVSAvoidproductivity
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies local quality by forming semiconductor layers with different electron affinities (first semiconductor layer with first electron affinity, second semiconductor layer with second electron affinity) in specific localized regions. This allows different transistor characteristics to be achieved in different areas of the same layer without requiring separate manufacturing processes, thereby maintaining design flexibility while avoiding increased manufacturing steps

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the electron affinity parameter of the semiconductor material to achieve different transistor characteristics. By selecting semiconductor materials with different electron affinities for different regions, the invention creates transistors with different electrical characteristics (such as threshold voltages) within the same manufacturing layer, resolving the contradiction between design flexibility and productivity

Inventive Principle:
Principle #35Parameter changes

2Reliability

If transistors with different electrical characteristics are separately manufactured, then electrical characteristics are improved, but the number of manufacturing steps increases, leading to decreased yield

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidyield
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent merges the manufacturing of transistors with different electrical characteristics into a single integrated process. By forming both first transistors (using first semiconductor layer) and second transistors (using second semiconductor layer) simultaneously in the same manufacturing step, the invention eliminates multiple separate manufacturing steps, thereby improving yield while maintaining the ability to achieve different electrical characteristics

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10115741B2Semiconductor device and electronic device
Publication Date: 2018.10.30 SEMICON ENERGY LAB CO LTD
  • US10115741B2 patent drawing
  • US10115741B2 patent drawing
  • US10115741B2 patent drawing

AI summary

To provide a semiconductor device capable of retaining data for a long period. The semiconductor device includes a memory circuit and a retention circuit. The memory circuit includes a first transistor, and the retention circuit includes a second transistor. The memory circuit is configured to write data by turning on the first transistor and to retain the data by turning off the first transistor. The retention circuit is configured to supply a first potential at which the first transistor is turned off to a back gate of the first transistor by turning on the second transistor and to retain the first potential by turning off the second transistor. Transistors having different electrical characteristics are used as the first transistor and the second transistor.