Semiconductor Back Surface Wiring Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional semiconductor apparatuses face issues with high parasitic capacitance due to the large area of through electrodes on the back surface, leading to signal propagation delays and decreased transmission speed, even when the through electrodes are not formed on the semiconductor substrate.
Innovation Solution
A semiconductor apparatus with a separation region, such as a resin or inorganic material, is introduced between the semiconductor substrate and the back surface side wiring, reducing parasitic capacitance by increasing the distance between the wiring and the substrate, and including a through wiring connecting the front and back surface side wittings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the through electrode area is increased to improve electrical connection, then the electrical connection is enhanced, but the parasitic capacitance increases causing signal propagation delay
Solution Approach 1:
The patent introduces a separation region that extends in the thickness direction (z-axis) of the semiconductor substrate, creating a three-dimensional spatial separation between the back surface side wiring and the semiconductor substrate. This vertical dimensionality change increases the distance between conductive elements without requiring lateral expansion, thus reducing parasitic capacitance while maintaining electrical connection reliability through the through electrode.
2Speed
If the distance between the back surface side wiring and the semiconductor substrate is increased to reduce parasitic capacitance, then the signal transmission speed is improved, but the chip thickness increases
Solution Approach 1:
The separation region is formed within the existing chip structure by removing a portion of the semiconductor substrate and filling it with insulating material. This nested approach integrates the separation function into the chip's internal architecture without requiring significant external thickness increase, as the separation region is contained within the overall chip envelope.
3Loss of time
If the separation region is introduced to reduce parasitic capacitance, then the signal propagation delay is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The separation region is formed during the substrate processing stage before the back surface side wiring is formed. By removing a portion of the semiconductor substrate and filling it with insulating material in advance, the patent creates a pre-prepared separation structure that simplifies subsequent wiring formation processes, as the wiring can be directly formed on the separation region without additional complex steps.
Data Source
AI summary
Please replace the currently pending Abstract with the following amended A parasitic capacitance of a wiring arranged on a back surface side of a semiconductor substrate is reduced. A semiconductor apparatus includes a semiconductor substrate, a back surface side wiring, a through wiring, and a separation region. In the semiconductor substrate, a semiconductor element and a front surface side wiring connected to the semiconductor element are arranged on a front surface side. The back surface side wiring is arranged on a back surface side of the semiconductor substrate. The through wiring is arranged in a through hole formed in the semiconductor substrate to connect the front surface side wiring and the back surface side wiring. The separation region is arranged between the semiconductor substrate and the back surface side wiring.