Semiconductor Device Fabrication with Backside Contacts and Fin Epitaxy
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to create smaller and more complex circuits while maintaining or improving electrical performance, particularly in the context of backside source/drain contacts in semiconductor devices.
Innovation Solution
The formation of a backside source/drain contact and epitaxial structures in semiconductor fins, which are connected to a multilayer interconnection structure, allowing for a more efficient and compact device design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional front-side source/drain contact formation is used, then manufacturing process is simple, but device flexibility and electrical performance are limited
Solution Approach 1:
The patent inverts the conventional approach by forming source/drain contacts on the backside of the semiconductor device rather than the front side. This allows the contact formation to occur before fin patterning, enabling greater architectural flexibility while managing complexity through process resequencing
2Productivity
If geometry size is reduced to increase functional density, then production efficiency improves and costs decrease, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary actions by forming the multilayer interconnection structure and source/drain contacts on the carrier substrate before transferring and patterning the fins. This sequencing allows precise contact formation at larger dimensions, which is then maintained through self-aligned processes during subsequent fin patterning, reducing precision requirements at critical steps
Data Source
AI summary
A method includes forming a first multilayer interconnection structure over a carrier substrate. A first interlayer dielectric (ILD) layer is deposited over the first multilayer interconnection structure. A first source/drain contact is formed in the first ILD layer. After forming the first source/drain contact, a semiconductive layer is formed over the first source/drain contact and the first ILD layer. The semiconductive layer is patterned to form a semiconductor fin over the first source/drain contact. A gate structure is formed across the semiconductor fin. The semiconductor fin is patterned to form a first recess and a second recess in the semiconductor fin, such that the first recess exposes the first source/drain contact. First and second source/drain epitaxial structures are respectively formed in the first and second recesses of the semiconductor fin such that the first source/drain epitaxial structure is electrically connected to the first source/drain contact.