Semiconductor Backside Layers for Thermal Stress and Warpage Control
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Solution Overview
Problem
Semiconductor chips face challenges in managing stress and warpage due to thermal expansion differences, leading to instability and inefficiencies in fabrication and attachment processes.
Innovation Solution
The implementation of backside layers (BLs) with varying coefficients of thermal expansion, which are designed to modify stress and shape by controlling curvature and surface contact, thereby enhancing thermal stability and reducing warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform metal layers are used across the chip, then fabrication is simpler, but thermal stress and warpage increase due to thermal expansion differences
Solution Approach 1:
The patent applies local quality by varying the thickness of metal layers at different locations on the chip. The first set of metal layers has a first thickness while the second set has a second thickness that is at least twice as large. This non-uniform distribution creates localized stress compensation zones that counteract thermal warpage while maintaining overall thermal stability.
Solution Approach 2:
The patent changes the physical parameter of metal layer thickness to manage thermal stress. By adjusting the thickness parameter of metal layers in different regions (first thickness vs. second thickness ≥ 2× first thickness), the patent optimizes the stress distribution across the chip to reduce warpage during thermal cycling.
2Stability of the object's composition
If thicker metal layers are used to reduce warpage, then thermal stability improves, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent segments the metal layer structure into multiple distinct sets (first set with first thickness, second set with second thickness ≥ 2× first thickness). This segmentation allows each layer to serve specific stress management functions, reducing overall warpage while maintaining a manageable structural complexity through systematic layering.
Solution Approach 2:
The patent creates a composite metal layer structure where different metal layers with different thicknesses and coefficients of thermal expansion are combined. The first set of metal layers has a first coefficient of thermal expansion while the second set has a second coefficient of thermal expansion, creating a composite structure that actively manages thermal stress.
3Shape
If multiple metal layers with different thicknesses are implemented, then warpage control improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent defines specific parameter relationships to simplify manufacturing precision requirements. The second thickness is specified as at least twice the first thickness, and the second coefficient of thermal expansion is no larger than half the first coefficient. These parameter relationships provide clear fabrication targets that improve warpage control while maintaining achievable manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
BLs improve thermal stability, reduce warpage, and increase the efficiency and reliability of chip attachment processes, allowing for more compact designs and higher yields in semiconductor fabrication.
Implementation Method 1
backside layers (BLs) with varying coefficients of thermal expansion, which are designed to modify stress and shape by controlling curvature and surface contact
Data Source
AI summary
A first chip comprises a first set of one or more metal layers having a first thickness and comprising at least one metal layer that has a first CTE. A first volume of the first chip is adjacent to the first set of one or more metal layers. A second volume of the first chip comprises one or more electronic or photonic structures, and a second set of one or more metal layers that has a second thickness at least twice as large as the first thickness. At least one metal layer in the second set has a second CTE. A set of one or more metal structures of the first chip is adjacent to the second volume and comprises at least one metal structure electrically connected to at least a portion of at least one metal layer in the second set of one or more metal layers.