Semiconductor Package Backside Nanopillar Heat Dissipation
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Solution Overview
Problem
As electrical power consumption increases in electronic integrated circuits, it is challenging to maintain the operating temperature of semiconductor devices within an acceptable range without increasing manufacturing costs and thickness by using traditional heat sinks or spreaders for heat dissipation.
Innovation Solution
A semiconductor package device is designed with nanoscale pillars or holes on the back surface of the electrical component, which acts as a heat dissipator, replacing the need for a heat sink and reducing the overall thickness and manufacturing cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a heat sink or spreader is bonded to the backside of the chip for heat dissipation, then heat dissipation performance is improved, but manufacturing cost and thickness increase
Solution Approach 1:
The patent applies porous silicon structure on the backside of the chip, creating a porous layer with high surface area to volume ratio that enhances heat dissipation. The porous structure is formed by anodization or electrochemical etching processes, creating a controlled porous morphology that improves thermal management without adding external heat sinks or spreaders, thereby reducing device thickness and manufacturing complexity
Solution Approach 2:
The patent transitions from two-dimensional heat dissipation (flat chip surface) to three-dimensional heat dissipation by creating vertical porous structures on the chip backside. This dimensional change increases the effective heat dissipation surface area without increasing the chip footprint or requiring additional external heat dissipation components, thus improving thermal performance while maintaining compact form factor
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The nanoscale features enhance heat dissipation performance while reducing the manufacturing cost and thickness of the semiconductor package device, effectively managing thermal issues without the need for additional heat dissipation structures.
Implementation Method 1
The nanoscale features enhance heat dissipation performance while reducing the manufacturing cost and thickness of the semiconductor package device
Data Source
AI summary
A semiconductor package device comprises a substrate, an electrical component and a package body. The electrical component is disposed on the substrate. The electrical component has an active surface facing toward the substrate and a back surface opposite to the active surface. The back surface has a first portion and a second portion surrounding the first portion. The first portion of the back surface of the electrical component includes a plurality of pillars. The package body is disposed on the substrate. The package body encapsulates the electrical component and exposes the back surface of the electrical component.