Semiconductor Backside Power Rails for Compact Low-Resistance Cells
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Solution Overview
Problem
Integrated circuits face challenges in achieving faster processing speeds, lower power consumption, and smaller size due to significant resistance in metal routing between active devices and power rails, particularly in analog cells with small geometry sizes.
Innovation Solution
The implementation of transistor structures with vias that couple doped regions to both front-side and back-side metal layers, reducing parasitic resistance and capacitance, and utilizing back-side power rails to connect front-side metal layers to power components, thereby minimizing cell area and enhancing operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal routing is used to connect active devices to power rails in analog cells, then electrical connection is established, but parasitic resistance increases significantly due to small geometry size
Solution Approach 1:
The patent utilizes the backside of the semiconductor substrate to route power connections, transitioning from planar (2D) routing to three-dimensional (3D) connectivity. By forming power rails and vias on the backside that extend through the substrate to connect with frontside active devices, the invention creates vertical connection paths that bypass the limitations of surface-level metal routing, thereby reducing parasitic resistance without increasing lateral footprint.
Solution Approach 2:
The patent implements a nested structure where backside power rails are positioned beneath frontside metal routing layers, and vias penetrate through intermediate dielectric layers to establish hierarchical connections. This nested arrangement allows multiple connection levels to coexist in a compact volume, enabling low-resistance power delivery paths while maintaining dense frontside circuit布局.
2Area of moving object
If cell size is reduced to achieve smaller device footprint, then integration density increases, but resistance of metal routing between active devices and power rail increases
Solution Approach 1:
The invention resolves the contradiction between small cell area and low routing resistance by exploiting the third dimension (vertical depth). Power rails are formed on the backside of the substrate and extend vertically through vias to connect with active devices on the frontside, creating short vertical connection paths that eliminate the need for long lateral metal routes, thus maintaining low resistance despite reduced cell footprint.
Solution Approach 2:
The patent introduces backside power rails as intermediary connection structures that mediate between frontside active devices and external power sources. These power rails serve as low-resistance intermediate nodes that collect current from multiple nearby active devices before routing it through substrate vias to external power connections, reducing the resistance burden on individual frontside metal traces.
3Power
If conventional frontside power routing is used, then power delivery is achieved, but cell area is increased due to routing requirements
Solution Approach 1:
The patent inverts the conventional power routing architecture by moving power rail formation from the frontside to the backside of the semiconductor substrate. Instead of routing power through metal layers on the same side as active devices, the invention delivers power through the substrate thickness from the backside, fundamentally reversing the traditional approach and enabling significant area savings on the frontside circuit layout.
Data Source
AI summary
A semiconductor device includes a first conductive line extending in a first direction on a front side of a semiconductor wafer, a first power rail extending in the first direction on a back side of the semiconductor wafer, and a first transistor including a first gate structure extending in a second direction perpendicular to the first direction, first and second active regions adjacent to the first gate structure, and a first channel region extending between the first and second active regions through the first gate structure. A first via is positioned between and electrically connects the first active region and the first conductive line, and a second via is positioned between and electrically connects the second active region and the first power rail.