Semiconductor Signal Routing With Backside Conductive Strips
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices shrink in size, the space for metal routing becomes insufficient, limiting the ability to effectively transfer signals between components.
Innovation Solution
The introduction of a semiconductor device design that incorporates a power grid structure on the backside of the substrate, allowing for the use of metal strips and conductive strips for signal connection, with isolation layers to manage signal routing and provide additional resources for signal transfer between source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If geometry size is decreased to increase functional density, then the number of interconnected devices per chip area is improved, but the space for metal routing becomes insufficient
Solution Approach 1:
The patent introduces a conductive strip extending from the source/drain region through the dielectric layer to connect with metal strips on the backside of the substrate. This three-dimensional routing approach moves signal paths from the traditional planar metal layers into the vertical dimension, effectively utilizing the substrate thickness and backside space for additional routing resources without occupying more chip area.
2Adaptability or versatility
If metal routing space is increased to improve signal connection capabilities, then signal transfer flexibility is improved, but device geometry size increases
Solution Approach 1:
The patent utilizes the backside of the substrate for metal strip placement, which is traditionally an unused or minimally used area. By inverting the routing approach and placing conductive elements on the backside rather than only on the front surface, the design achieves additional routing capacity without increasing the chip footprint, effectively turning the backside space into a valuable resource for signal interconnection.
Data Source
AI summary
A semiconductor device, including: a transistor layer, including a first active region configured to be a source/drain terminal of a first transistor and a second active region configured to be a source/drain terminal of a second transistor; a dielectric layer, disposed on the source/drain terminals of the first and second transistors; a conductive strip, included in the dielectric layer and extending from the first active region toward the second active region for signal connection.