Semiconductor Layout With Backside Vias for Lower Source Inductance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with finger-shaped electrodes, arranging multiple unit FETs in the extending direction of the electrodes can lead to increased source inductance and gate-source parasitic capacitance, degrading high-frequency characteristics.
Innovation Solution
The semiconductor device incorporates a substrate with a main surface and a back surface, featuring multiple transistors with specific electrode configurations and interconnections, including via holes for equalizing source inductances and reducing parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple unit FETs are arranged in the extending direction of the electrodes, then the device can achieve higher integration density, but the source inductance increases and high-frequency characteristics deteriorate
Solution Approach 1:
The patent transitions from one-dimensional linear arrangement of FETs to a two-dimensional layout where source electrodes are arranged in the extending direction and via holes are positioned at both ends in the width direction. This dimensional change allows current to flow through multiple parallel paths (front and back surfaces), reducing source inductance while maintaining high integration density.
Solution Approach 2:
The source electrode is segmented into multiple regions with via holes distributed at both ends in the width direction. This segmentation creates multiple current paths that reduce the overall source inductance, allowing the device to maintain high integration density without sacrificing high-frequency performance.
2Productivity
If multiple unit FETs are arranged in the extending direction of the electrodes, then more transistors can be packed into the device, but gate-source parasitic capacitance increases
Solution Approach 1:
By utilizing the third dimension (via holes penetrating the substrate) and arranging electrodes in both length and width directions, the patent reduces the overlapping area between gate and source electrodes in any given plane. This dimensional approach allows more transistors to be packed while minimizing parasitic capacitance generation.
Solution Approach 2:
The gate and source electrodes are segmented into multiple finger-shaped units arranged in a grid pattern, which distributes the parasitic capacitance across multiple smaller interfaces rather than having one large overlapping area, thereby reducing total parasitic capacitance while increasing transistor count.
3Reliability
If via holes are provided at both ends in the width direction, then source inductance is reduced, but device complexity increases
Solution Approach 1:
The via holes serve multiple functions: they electrically connect source electrodes on opposite surfaces, reduce source inductance by creating parallel current paths, and are strategically positioned at both ends to optimize current distribution. This multi-functionality achieves inductance reduction without proportionally increasing device complexity.
Solution Approach 2:
The via holes are positioned to create equipotential regions at both ends of the source electrode in the width direction, balancing the current distribution and minimizing inductance. This symmetric arrangement achieves optimal electrical performance with a regular, manufacturable pattern.
Data Source
AI summary
A semiconductor device includes a substrate having a main surface and a back surface, and first and second transistors. A first gate wiring is provided on the main surface a disposed in a first source electrode of the first transistor when viewed from a direction, and is electrically connected to a first gate electrode thereof. The second source electrode is interposed between a second gate electrode of the second transistor and a first gate wiring. A back metal layer is provided on the back surface and is electrically connected to the first source electrode and a second source electrode of the second transistor through a first via hole and a second via hole which overlap the first source electrode and the second source electrode, respectively, when viewed in a thickness direction of the substrate.